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enhanced a/d flash type 8-bit mcu with eeprom HT66F60A ht66f70a revision: v1.00 date: ?a??? ?0? ?01? ?a??? ?0? ?01?
rev. 1.00 ? ?a??? ?0? ?01? rev. 1.00 ? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom table of contents eates cpu featu?es ........................................................................................................................ 7 pe?ip?e?al featu?es ................................................................................................................ 7 gene?al des??iption ......................................................................................... 8 sele?tion table ................................................................................................. 8 blo?k diag?am .................................................................................................. 9 pin assignment .............................................................................................. 10 pin des??iption .............................................................................................. 1? absolute ?aximum ratings .......................................................................... 18 d.c. c?a?a?te?isti?s ....................................................................................... 18 a.c. c?a?a?te?isti?s ....................................................................................... ?1 a/d conve?te? c?a?a?te?isti?s ...................................................................... ?? lvd & lvr ele?t?i?al c?a?a?te?isti?s .......................................................... ?? compa?ato? ele?t?i?al c?a?a?te?isti?s ........................................................ ?? powe? on reset ele?t?i?al c?a?a?te?isti?s ................................................. ?? system a???ite?tu?e ...................................................................................... ?4 clo?king and pipelining ......................................................................................................... ?4 p?og?am counte? ................................................................................................................... ?5 sta?k ..................................................................................................................................... ?6 a?it?meti? and logi? unit C alu ........................................................................................... ?6 flas? p?og?am ?emo?y ................................................................................. ?7 st?u?tu?e ................................................................................................................................ ?7 spe? ial ve?to?s ..................................................................................................................... ?8 look-up table ........................................................................................................................ ?8 table p ?og?am example ........................................................................................................ ?9 in ci??uit p?og?amming C icp ............................................................................................... ?0 on-c?ip debug suppo?t C ocds ......................................................................................... ?1 in appli ?ation p?og?amming C iap ........................................................................................ ?1 data ?emo?y .................................................................................................. ?9 st?u?tu?e ................................................................................................................................ ?9 gene?al pu?pose data ?emo?y ............................................................................................ 40 spe?ial pu?pose data ?emo?y ............................................................................................. 40 spe?ial fun?tion registe? des??iption ........................................................ 4? indi?e? t add?essing registe?s C iar0? iar1 ......................................................................... 4? ?emo?y pointe?s C ?p0? ?p1 .............................................................................................. 4? bank pointe? C bp ................................................................................................................. 4? a??umulato? C acc ............................................................................................................... 4? p?og?am counte? low registe? C pcl .................................................................................. 44 look-up table registe ? s C tblp ? tbhp ? tblh ..................................................................... 44 status registe? C status .................................................................................................... 44
rev. 1.00 ? ?a??? ?0? ?01? rev. 1.00 ? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom eeprom data memory .................................................................................. 46 eepro? data ?emo?y st?u?tu?e ........................................................................................ 46 eepro? registe?s .............................................................................................................. 46 reading data f?om t?e eepro? ......................................................................................... 47 w ?iting data to t?e eepro? ................................................................................................ 48 w ?ite p?ote?tion ..................................................................................................................... 48 eepro? inte??upt ................................................................................................................ 48 p?og?amming conside?ations ................................................................................................ 48 p?og?amming examples ........................................................................................................ 49 oscillator ........................................................................................................ 50 os?illato? ove?view ............................................................................................................... 50 system clock confgurations ................................................................................................ 50 exte?nal c?ystal/ce?ami? os?illato? C hxt ........................................................................... 51 exte?nal rc os?illato? C erc ............................................................................................... 5? inte?nal hig? speed rc os?illato? C hirc ........................................................................... 5? exte?nal ??.768khz c?ystal os?illato? C lxt ........................................................................ 5? inte?nal low speed os?illato? C lirc ................................................................................... 54 supplementa?y os?illato?s .................................................................................................... 54 operating modes and system clocks ......................................................... 55 system clo?k ........................................................................................................................ 55 system ope?ation ?odes ...................................................................................................... 56 cont?ol registe? .................................................................................................................... 57 fast wake-up ........................................................................................................................ 60 ope?ating ?ode swit??ing .................................................................................................... 61 nor? al ?ode to slow ?ode swit??ing ........................................................................... 6? slow ?ode to nor? al ?ode swit??ing ........................................................................... 6? ente?ing t?e sleep0 ?ode .................................................................................................. 64 ente?ing t?e sleep1 ?ode .................................................................................................. 64 ente?ing t?e idle0 ?ode ...................................................................................................... 64 ente?ing t?e idle1 ?ode ...................................................................................................... 65 standby cu??ent conside?ations ........................................................................................... 65 wake-up ................................................................................................................................ 66 p?og?amming conside?ations ................................................................................................ 66 watchdog timer ............................................................................................. 67 wat ?? dog time? clo?k sou??e .............................................................................................. 67 wat ?? dog time? cont?ol registe? ......................................................................................... 67 wat ?? dog time? ope?ation ................................................................................................... 68 reset and initialisation .................................................................................. 70 reset fun?tions .................................................................................................................... 70 reset initial conditions ......................................................................................................... 74
rev. 1.00 4 ?a??? ?0? ?01? rev. 1.00 5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom input/output ports ......................................................................................... 78 pull-?ig? resisto?s ................................................................................................................ 80 po? t a wake-up ..................................................................................................................... 80 i/o po?t cont?ol registe?s ..................................................................................................... 80 pin-s?a?ed fun?tions ............................................................................................................ 80 i/o pin st?u?tu?es .................................................................................................................. 9? p?og?amming conside?ations ................................................................................................ 94 timer modules C tm ...................................................................................... 94 int?odu?tion ........................................................................................................................... 94 t? ope?ation ........................................................................................................................ 95 t? clo?k sou??e ................................................................................................................... 95 t? inte??upts ......................................................................................................................... 95 t? exte?nal pins ................................................................................................................... 96 t? input/output pin cont?ol ................................................................................................. 97 p?og?amming conside?ations ................................................................................................ 98 compact type tm C ctm .............................................................................. 99 compa?t t? ope?ation ......................................................................................................... 99 compa? t type t? registe? des??iption .............................................................................. 100 compa? t type t? ope?ating ?odes .................................................................................. 104 compa?e ?at?? output ?ode ............................................................................................. 104 time ?/counte? ?ode ........................................................................................................... 107 pw? output ?ode .............................................................................................................. 107 standard type tm C stm ............................................................................. 110 standa?d t? ope?ation ........................................................................................................ 110 standa? d type t? registe? des??iption .............................................................................. 111 standa? d type t? ope?ating ?odes ................................................................................... 115 compa?e ?at?? output ?ode .............................................................................................. 115 time ?/counte? ?ode ............................................................................................................ 118 pw? output ?ode ............................................................................................................... 118 single pulse ?ode .............................................................................................................. 1?1 captu?e input ?ode ............................................................................................................ 1?? enhanced type tm C etm ........................................................................... 125 en?an? ed t? ope?ation ..................................................................................................... 1?5 en?an? ed type t? registe? des??iption ............................................................................ 1?6 en?an? ed type t? ope?ating ?odes ................................................................................. 1?? compa?e output ?ode ........................................................................................................ 1?? time ?/counte? ?ode ........................................................................................................... 1?8 pw? output ?ode .............................................................................................................. 1?8 single pulse ?ode .............................................................................................................. 144 captu?e input ?ode ............................................................................................................ 146
rev. 1.00 4 ?a??? ?0? ?01? rev. 1.00 5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom aanlog to digital converter ........................................................................ 149 a/d ove?view ...................................................................................................................... 149 a/d conve?te? registe? des??iption .................................................................................... 149 a/d ope?ation ..................................................................................................................... 15? a/d input pins ..................................................................................................................... 154 summa? y of a/d conve?sion steps ..................................................................................... 154 p?og?amming conside?ations .............................................................................................. 156 a/d t ?ansfe? fun?tion ......................................................................................................... 156 a/d p?og?amming example ................................................................................................. 157 comparators ................................................................................................ 159 compa?ato? ope?ation ........................................................................................................ 159 compa?ato? registe?s ......................................................................................................... 160 compa?ato? inte??upt ........................................................................................................... 16? p?og?amming conside?ations .............................................................................................. 16? serial interface module C sim ..................................................................... 162 spi inte?fa?e ....................................................................................................................... 16? spi registe?s ...................................................................................................................... 164 spi communi?ation ............................................................................................................ 167 i ? c inte?fa?e ........................................................................................................................ 169 i ? c inte?fa?e ope?ation ........................................................................................................ 169 i ? c registe?s ....................................................................................................................... 170 i ? c bus communi?ation ...................................................................................................... 174 i ? c bus sta?t signal ............................................................................................................. 175 slave add?ess ..................................................................................................................... 175 i ? c bus read/w ?ite signal .................................................................................................. 176 i ? c bus slave add ? ess a?knowledge signal ....................................................................... 176 i ? c bus data and a ?knowledge signal ............................................................................... 176 peripheral clock output .............................................................................. 179 pe?ip?e?al clo?k ope?ation ................................................................................................. 179 pe?ip?e?al clo?k registe?s .................................................................................................. 180 serial interface C spia ................................................................................. 181 spia inte ?fa?e ope?ation .................................................................................................... 181 spia ?egiste?s ..................................................................................................................... 18? spia communi ?ation .......................................................................................................... 185 spia bus enable/disable .................................................................................................... 187 spia ope ?ation ................................................................................................................... 187 e??o? dete?tion .................................................................................................................... 188
rev. 1.00 6 ?a??? ?0? ?01? rev. 1.00 7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom interrupts ...................................................................................................... 189 inte??upt registe?s ............................................................................................................... 189 inte??upt ope?ation .............................................................................................................. ?00 exte?nal inte??upt ................................................................................................................. ?01 compa?ato? inte??upt ........................................................................................................... ?01 ?ulti-fun?tion inte??upt ........................................................................................................ ?01 a/d conve?te? inte??upt ....................................................................................................... ?0? time base inte ??upt ............................................................................................................. ?0? se?ial inte?fa?e ?odule inte??upts ....................................................................................... ?04 spia inte ?fa?e inte??upt ....................................................................................................... ?04 exte?nal pe?ip?e?al inte??upt ............................................................................................... ?04 eepro? inte??upt .............................................................................................................. ?05 lvd inte ??upt ....................................................................................................................... ?05 t? inte??upts ....................................................................................................................... ?05 inte?? upt wake-up fun?tion ................................................................................................. ?06 p?og?amming conside?ations .............................................................................................. ?06 low voltage detector C lvd ....................................................................... 207 lvd registe ? ....................................................................................................................... ?07 lvd ope ?ation ..................................................................................................................... ?08 scom function for lcd .............................................................................. 209 lcd ope?ation .................................................................................................................... ?09 lcd bias cont?ol ................................................................................................................ ?09 confguration options ................................................................................. 210 application circuits ..................................................................................... 210 instruction set ............................................................................................... 211 int?odu?tion .......................................................................................................................... ? 11 inst?u? tion timing ................................................................................................................. ? 11 ? oving and t ?ansfe??ing data .............................................................................................. ? 11 a?it?meti? ope?ations ........................................................................................................... ? 11 logi?al and rotate ope?ation ............................................................................................. ?1? b?an??es and cont? ol t ?ansfe? ........................................................................................... ?1? bit ope?ations ..................................................................................................................... ?1? table read ope ?ations ....................................................................................................... ?1? ot?e? ope?ations ................................................................................................................. ?1? instruction set summary ............................................................................ 213 table conventions ............................................................................................................... ?1? extended inst?u?tion set ..................................................................................................... ?15 instruction defnition ................................................................................... 217 ([whqghg,qvwuxfwlrqhqlwlrq ........................................................................................... ??7 package information ................................................................................... 234 48-pin lqfp (7mm7mm) outline dimensions .................................................................. ??5 64-pin lqfp (7mm7mm) outline dimensions .................................................................. ??6
rev. 1.00 6 ?a??? ?0? ?01? rev. 1.00 7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom features cpu features ? op erating voltage: f sys =8mhz: 2.2v~5.5v f sys = 12 mhz: 2. 7 v~5.5v f sys = 16 mhz: 4.5 v~5.5v ? up to 0.25s instruction cycle with 16mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? five oscillators: external crystal -- hxt external 32.768khz crystal -- lxt external rc -- erc internal rc -- hirc internal 32khz rc -- lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 8mhz ocilllator requires no external components ? all instructions executed in 1~3 instruction cycles ? table read instructions ? 114 powerful instructions ? u p to 16-level subroutine nesting ? bit manip ulation instruction peripheral features ? flash program memory: 16k16~32k16 ? data memory: 10248~20488 ? eeprom memory: 1288 ? in application programming function ? watchdog timer function ? up to 61 bidirectional i/o lines ? software controlled 4-scom lines lcd driver with 1/2 bias ? multiple pin-shared external interrupts ? multiple timer module for time measure, input capture, compare match output, pwm output or single pulse output function ? serial interfaces module C sim for spi or i 2 c ? single sefal spi interface C spia ? dual comparator functions ? dual time-base functions for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? low voltage reset function ? low voltage detect function ? wide range of available package types ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? eeprom data memory can be re-programmed up to 1,000,000 times ? eeprom data memor y data retention > 10 years
rev. 1.00 8 ?a??? ?0? ?01? rev. 1.00 9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom general description the ht66fx0a series of devices are flash memory a/d type 8-bit high performance risc architecture microcontrollers, designed for a wide range of applications. offering users the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter and dual comparator functions. multiple and extremely flexible timer modules provide timing, pulse generation and pwm generation functions. communication with the outside world is catered for by including fully integrated spi or i 2 c interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protective features such as an internal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt, lxt, erc, hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features, time-base functions along with many other features ensure that the devices will fnd excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. selection table most features are common to all devices. the main features distinguishing them are program memory and data memory capacity. the following table summarises the main features of each device. part no. program memory data memory data eeprom i/o external interrupt a/d converter timer module sim spia time base comparators stacks package HT66F60A 16k 16 10?4 8 1?8 8 61 4 1?-bit 1? 10-bit ct? ? 16-bit st? ? 10-bit et? 1 ? ? 16 48/64 lqfp ht66f70a ??k 16 ?048 8 1?8 8 61 4 1?-bit 1? 10-bit ct? ? 16-bit st? ? 10-bit et? 1 ? ? 16 48/64 lqfp note: as devices exist in more than one package format, the table refects the situation for the package with the most pins.
rev. 1.00 8 ?a??? ?0? ?01? rev. 1.00 9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom block diagram
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rev. 1.00 10 ?a??? ?0? ?01? rev. 1.00 11 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom pin assignment p h 0 / t p 0 / t p 0 b / a n 0 / v r e f / c 0 x pf 1 / an 11/ c 1 p pf 0 / an 10/ c 1 n pe7 / an 9 / int 1 pe6 / an 8 / int 0 vss vdd pb 4 / xt ? pb ? / xt 1 vss ? pb 1 / osc 1 pb ? / osc ? pe 5 / tp ? / tp ? b p e 4 / t p 1 b / t p 1 b b / t p 1 i b p b 0 / r e s p f ? p e ? / s d o a / t c k ? p e ? / s d i a / i n t ? p e 1 / s c k a / i n t 1 p c 0 / t p 1 b / t p 1 b b / t p 1 i b / s c o ? 0 p c 1 / t p 1 b / t p 1 b b / t p 1 i b / s c o ? 1 p c 7 / s c o ? ? / t p 1 a / t p 1 i a p c 6 / s c o ? ? / t p 0 / t p 0 b p d 5 / t p 0 / t p 0 b pd 4 / tp ? / tp ? b / tp ? i pd ? / tp ? / tp ? b / sdo / sck / scl / tck 1 pd ? / sdi / sda / tck 0 pd 1 / tp ? / tp ? b / tp ? i / sdo / sck / scl pd 0 / tp ? / tp ? b / scs / tck ? pc 5 / int ? / tp 0 / tp 0 b / tp 1 b / tp 1 bb / tp 1 ib / int 1 / pck pc 4 / int ? / tck ? / tp ? / tp ? b / tp ? i / int 0 / pint pc ? / pint / tp ? / tp ? b / tp ? i / c 1 x pc ? / pck / tck ? / c 0 x pd 7 / scs pd 6 / sck / scl pb 7 / sdi / sda p b 6 / s d o p a ? p a 0 p b 5 / s c s 1? 14 15 16 17 18 19 ?0 ?1 ?? ?? ?4 p a 7 / s c k / s c l / a n 7 p a 6 / s d i / s d a / a n 6 p a 5 / s d o / a n 5 / c 1 x p a 4 / i n t 1 / t c k 1 / a n 4 p a ? / i n t 0 / a n ? / c 0 n p h 1 / t c k 0 / a n ? / c 0 p p a 1 / t p 1 a / t p 1 i a / a n 1 1 ? ? 4 5 6 7 8 9 10 11 1? ?7 ?6 ?5 ?8 ?9 ?0 ?1 ?? ?? ?4 ?5 ?6 48 47 46 45 44 4? 4? 41 40 ?9 ?8 ?7 p e 0 / s c s a / i n t 0 ht 66f 60 a / ht 66f 70 a 48 lqfp -a ph 0 / tp 0 / tp 0 b / an 0 / vref / c 0 x 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 15 16 pf 1 / an 11 / c 1 p pf 0 / an 10 / c 1 n pe 7 / an 9 / int 1 pe 6 / an 8 / int 0 pf 6 vss vdd pb4 / xt ? pb? / xt 1 vss ? pb1 / osc 1 pb? / osc ? pf 4 pf ? pe 5 / tp ? / tp ? b p e 4 / t p 1 b / t p 1 b b / t p 1 i b p b 0 / r e s p f 5 p f ? p e ? / s d o a / t c k ? p e ? / s d i a / i n t ? p e 1 / s c k a / i n t 1 p c 0 / t p 1 b / t p 1 b b / t p 1 i b / s c o ? 0 p c 1 / t p 1 b / t p 1 b b / t p 1 i b / s c o ? 1 p c 7 / s c o ? ? / t p 1 a / t p 1 i a p c 6 / s c o ? ? / t p 0 / t p 0 b p g 0 / c 0 x p g 1 / c 1 x p d 5 / t p 0 / t p 0 b p d 4 / t p ? / t p ? b / t p ? i ?9 ?8 ?7 ?6 ?5 ?4 ?? 40 41 4? 4? 44 45 46 47 48 pg 4 / tp 4 / tp 4 b / tp 4 i pg ? / tp 4 / tp 4 b / tp 4 i pg ? / tck 4 pd ? / tp ? / tp ? b / sdo / sck / scl / tck 1 pd ? / sdi / sda / tck 0 pd 1 / tp ? / tp ? b / tp ? i / sdo / sck / scl pd 0 / tp ? / tp ? b / scs / tck ? pc 5 / int ? / tp 0 / tp 0 b / tp 1 b / tp 1 bb / tp 1 ib / int 1 / pck pc 4 / int ? / tck ? / tp ? / tp ? b / tp ? i / int 0 / pint pc ? / pint / tp ? / tp ? b / tp ? i / c 1 x pc ? / pck / tck ? / c 0 x pd 7 / scs pd 6 / sck / scl pb 7 / sdi / sda pb 6 / sdo ph 5 / sdoa p h 4 / s d i a p a ? p a 0 p h ? / s c k a p h ? / s c s a p g 7 / t p 5 / t p 5 b / t p 5 i p g 6 / t p 5 / t p 5 b / t p 5 i p g 5 / t c k 5 p b 5 / s c s 17 18 19 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 ?0 ?1 ?? 64 6? 6? 61 60 59 58 57 56 55 54 5? 5? 51 50 49 p a 7 / s c k / s c l / a n 7 p a 6 / s d i / s d a / a n 6 p a 5 / s d o / a n 5 / c 1 x p a 4 / i n t 1 / t c k 1 / a n 4 p a ? / i n t 0 / a n ? / c 0 n p h 1 / t c k 0 / a n ? / c 0 p p a 1 / t p 1 a / t p 1 i a / a n 1 p e 0 / s c s a / i n t 0 ht 66 f 60a / ht 66 f 70 a 64 lqfp -a
rev. 1.00 10 ?a??? ?0? ?01? rev. 1.00 11 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom p h 0 / t p 0 / t p 0 b / a n 0 / v r e f / c 0 x pf 1 / an 11/ c 1 p pf 0 / an 10/ c 1 n pe7 / an 9 / int 1 pe6 / an 8 / int 0 vss vdd pb 4 / xt ? pb ? / xt 1 vss ? pb 1 / osc 1 pb ? / osc ? pe 5 / tp ? / tp ? b p e 4 / t p 1 b / t p 1 b b / t p 1 i b p b 0 / r e s p f ? p e ? / s d o a / t c k ? p e ? / s d i a / i n t ? p e 1 / s c k a / i n t 1 p c 0 / t p 1 b / t p 1 b b / t p 1 i b / s c o ? 0 p c 1 / t p 1 b / t p 1 b b / t p 1 i b / s c o ? 1 p c 7 / s c o ? ? / t p 1 a / t p 1 i a p c 6 / s c o ? ? / t p 0 / t p 0 b p d 5 / t p 0 / t p 0 b pd 4 / tp ? / tp ? b / tp ? i pd ? / tp ? / tp ? b / sdo / sck / scl / tck 1 pd ? / sdi / sda / tck 0 pd 1 / tp ? / tp ? b / tp ? i / sdo / sck / scl pd 0 / tp ? / tp ? b / scs / tck ? pc 5 / int ? / tp 0 / tp 0 b / tp 1 b / tp 1 bb / tp 1 ib / int 1 / pck pc 4 / int ? / tck ? / tp ? / tp ? b / tp ? i / int 0 / pint pc ? / pint / tp ? / tp ? b / tp ? i / c 1 x pc ? / pck / tck ? / c 0 x pd 7 / scs pd 6 / sck / scl pb 7 / sdi / sda p b 6 / s d o p a ? / i c p c k / o c d s c k p a 0 / i c p d a / o c d s d a p b 5 / s c s 1? 14 15 16 17 18 19 ?0 ?1 ?? ?? ?4 p a 7 / s c k / s c l / a n 7 p a 6 / s d i / s d a / a n 6 p a 5 / s d o / a n 5 / c 1 x p a 4 / i n t 1 / t c k 1 / a n 4 p a ? / i n t 0 / a n ? / c 0 n p h 1 / t c k 0 / a n ? / c 0 p p a 1 / t p 1 a / t p 1 i a / a n 1 1 ? ? 4 5 6 7 8 9 10 11 1? ?7 ?6 ?5 ?8 ?9 ?0 ?1 ?? ?? ?4 ?5 ?6 48 47 46 45 44 4? 4? 41 40 ?9 ?8 ?7 p e 0 / s c s a / i n t 0 ht 66 v70a 48 lqfp -a ph 0 / tp 0 / tp 0 b / an 0 / vref / c 0 x 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 15 16 pf 1 / an 11 / c 1 p pf 0 / an 10 / c 1 n pe 7 / an 9 / int 1 pe 6 / an 8 / int 0 pf 6 vss vdd pb4 / xt ? pb? / xt 1 vss ? pb1 / osc 1 pb? / osc ? pf 4 pf ? pe 5 / tp ? / tp ? b p e 4 / t p 1 b / t p 1 b b / t p 1 i b p b 0 / r e s p f 5 p f ? p e ? / s d o a / t c k ? p e ? / s d i a / i n t ? p e 1 / s c k a / i n t 1 p c 0 / t p 1 b / t p 1 b b / t p 1 i b / s c o ? 0 p c 1 / t p 1 b / t p 1 b b / t p 1 i b / s c o ? 1 p c 7 / s c o ? ? / t p 1 a / t p 1 i a p c 6 / s c o ? ? / t p 0 / t p 0 b p g 0 / c 0 x p g 1 / c 1 x p d 5 / t p 0 / t p 0 b p d 4 / t p ? / t p ? b / t p ? i ?9 ?8 ?7 ?6 ?5 ?4 ?? 40 41 4? 4? 44 45 46 47 48 pg 4 / tp 4 / tp 4 b / tp 4 i pg ? / tp 4 / tp 4 b / tp 4 i pg ? / tck 4 pd ? / tp ? / tp ? b / sdo / sck / scl / tck 1 pd ? / sdi / sda / tck 0 pd 1 / tp ? / tp ? b / tp ? i / sdo / sck / scl pd 0 / tp ? / tp ? b / scs / tck ? pc 5 / int ? / tp 0 / tp 0 b / tp 1 b / tp 1 bb / tp 1 ib / int 1 / pck pc 4 / int ? / tck ? / tp ? / tp ? b / tp ? i / int 0 / pint pc ? / pint / tp ? / tp ? b / tp ? i / c 1 x pc ? / pck / tck ? / c 0 x pd 7 / scs pd 6 / sck / scl pb 7 / sdi / sda pb 6 / sdo ph 5 / sdoa p h 4 / s d i a p a ? / i c p c k / o c d s c k p a 0 / i c p d a / o c d s d a p h ? / s c k a p h ? / s c s a p g 7 / t p 5 / t p 5 b / t p 5 i p g 6 / t p 5 / t p 5 b / t p 5 i p g 5 / t c k 5 p b 5 / s c s 17 18 19 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 ?0 ?1 ?? 64 6? 6? 61 60 59 58 57 56 55 54 5? 5? 51 50 49 p a 7 / s c k / s c l / a n 7 p a 6 / s d i / s d a / a n 6 p a 5 / s d o / a n 5 / c 1 x p a 4 / i n t 1 / t c k 1 / a n 4 p a ? / i n t 0 / a n ? / c 0 n p h 1 / t c k 0 / a n ? / c 0 p p a 1 / t p 1 a / t p 1 i a / a n 1 p e 0 / s c s a / i n t 0 ht 66 v70 a 64 lqfp -a note: 1. if the pin-shared pin functions have multiple outputs simultaneously, the pin-shared function is determined by the corresponding software control bits except the functions determined by the confguration options. 2. the ht66vx0a device is the ev chip of the ht66fx0a series of devices. it supports the on-chip debug function for debugging during development using the ocdsda and ocdsck pins connected to the holtek ht-ide development tools.
rev. 1.00 1? ?a??? ?0? ?01? rev. 1.00 1? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom pin description pad name function opt i/t o/t description pa0/icpda/ ocdsda pa0 pawu papu st c?os gene ? al pu? pose i/o. registe ? enabled pull-up and wake-up icpda st c?os icp data/add ?ess ocdsda st c?os ocds data/add?ess? fo? ev ??ip only pa1/tp1a/ tp1ia/an1 pa1 pawu papu pas0 st c?os gene ? al pu? pose i/o. registe ? enabled pull-up and wake-up tp1a pas0 c?os t? 1 a output tp1ia ifs? st t? 1 a input an1 pas0 an a/d conve?te? analog input pa ?/icpck/ ocdsck pa ? pawu papu st c?os gene ? al pu? pose i/o. registe ? enabled pull-up and wake-up icpck st c?os icp clo ?k pin ocdsck st ocds clo?k pin? fo? ev ??ip only pa ?/int0/ an?/c0n pa ? pawu papu pas1 st c?os gene ? al pu? pose i/o. registe ? enabled pull-up and wake-up int0 integ intc0 ifs0 st exte?nal inte??upt 0 an? pas1 an a/d conve?te? analog input c0n pas1 an compa?ato? 0 inve?ting input pa4/int1/ tck1/an4 pa4 papu pawu pas ? st c?os gene ? al pu? pose i/o. registe ? enabled pull-up and wake-up int1 integ intc0 ifs0 st exte?nal inte??upt 1 tck1 ifs1 st t?1 input an4 pas1 an a/d conve?te? analog input pa5/sdo/ an5/c1x pa5 pawu papu pas ? st c?os gene ? al pu? pose i/o. registe ? enabled pull-up and wake-up sdo pas ? c?os spi data output an5 pas ? an a/d conve?te? analog input c1x pas ? c?os compa?ato? 1 output pa6/sdi/ sda/an6 pa6 pawu papu pas ? st c?os gene ? al pu? pose i/o. registe ? enabled pull-up and wake-up sdi pas ? ifs4 st spi data input sda pas ? ifs4 st n?os i ? c data line an6 pas ? an a/d conve?te? analog input pa7/sck/ scl/an7 pa7 pawu papu pas ? st c?os gene ? al pu? pose i/o. registe ? enabled pull-up and wake-up sck pas ? ifs4 st c?os spi se?ial ?lo?k scl pas ? ifs4 st n?os i ? c ?lo?k line an7 pas ? an a/d conve?te? analog input
rev. 1.00 1? ?a??? ?0? ?01? rev. 1.00 1? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom pad name function opt i/t o/t description pb0/ res pb0 pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up res co st reset pin pb1/osc1 pb1 pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up osc1 co hxt hxt/erc os?illato? pin & ec mode input pin pb?/osc? pb? pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up osc? co hxt hxt os ?illato? pin pb?/xt1 pb? pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up xt1 co lxt lxt os ?illato? pin pb4/xt? pb4 pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up xt? co lxt lxt os ?illato? pin pb5/ scs pb5 pbpu pbs? st c?os gene?al pu?pose i/o. registe? enabled pull-up scs pbs? ifs4 st c?os spi slave sele?t pb6/sdo pb6 pbpu pbs? st c?os gene ? al pu? pose i/o. registe ? enabled pull-up and wake-up sdo pbs? c?os spi data output pb7/sdi/sda pb7 pbpu pbs? st c?os gene ? al pu? pose i/o. registe ? enabled pull-up and wake-up sdi pbs? ifs4 st spi data input sda pbs? ifs4 st n?os i ? c data line pc0/tp1b/ tp1bb/tp1ib/ sco?0 pc0 pcpu pcs0 st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1b pcs0 c?os t?1 b output tp1bb pcs0 c?os t?1 inve?ted b output tp1ib ifs? st t?1 b input sco?0 pcs0 sco? lcd ?ommon output pc1/tp1b/ tp1bb/tp1ib/ sco?1 pc1 pcpu pcs0 st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1b pcs0 c?os t?1 b output tp1bb pcs0 c?os t?1 inve?ted b output tp1ib ifs? st t?1 b input sco?1 pcs0 sco? lcd ?ommon output pc?/pck/ tck?/c0x pc? pcpu pcs1 st c?os gene?al pu?pose i/o. registe? enabled pull-up pck pcs1 c?os pe?ip?e?al ?lo?k output tck? ifs1 st t?? input c0x pcs1 c?os compa?ato? 0 output pc?/ pint /tp?/ tp?b/tp?i/c1x pc? pcpu pcs1 st c?os gene?al pu?pose i/o. registe? enabled pull-up pint ifs0 st pe?ip?e?al inte??upt tp? pcs1 c?os t?? output tp?b pcs1 c?os t?? inve?ted output tp?i ifs? st t?? input c1x pcs1 c?os compa?ato? 1 output
rev. 1.00 14 ?a??? ?0? ?01? rev. 1.00 15 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom pad name function opt i/t o/t description pc4/int?/tck?/ tp?/tp?b/tp?i/ int0/ pint pc4 pcpu pcs? st c?os gene?al pu?pose i/o. registe? enabled pull-up int? integ intc? ifs0 st exte?nal inte??upt ? tck? ifs1 st t?? input tp? pcs1 c?os t?? output tp?b pcs1 c?os t?? inve?ted output tp?i ifs? st t?? input int0 integ intc0 ifs0 st exte?nal inte??upt 0 pint ifs0 st pe?ip?e?al inte??upt pc5/int?/tp0/ tp0b/tp1b/ tp1bb/tp1ib/ int1/pck pc5 pcpu pcs? st c?os gene?al pu?pose i/o. registe? enabled pull-up int? integ intc? st exte?nal inte??upt ? tp0 pcs? c?os t?0 output tp0b pcs? c?os t?0 inve?ted output tp1b pcs? c?os t?1 b output tp1bb pcs? c?os t?1 inve?ted b output tp1ib ifs? st t?1 b input int1 integ intc0 ifs0 st exte?nal inte??upt 1 pck pcs? c?os pe?ip?e?al ?lo?k output pc6/sco??/ tp0/tp0b pc6 pcpu pcs? st c?os gene?al pu?pose i/o. registe? enabled pull-up sco?? pcs? sco? lcd ?ommon output tp0 pcs? c?os t?0 output tp0b pcs? c?os t?0 inve?ted output pc7/sco??/ tp1a/tp1ia pc7 pcpu pcs? st c?os gene?al pu?pose i/o. registe? enabled pull-up sco?? pcs? sco? lcd ?ommon output tp1a pcs? c?os t? 1 a output tp1ia ifs? st t? 1 a input pd0/tp?/tp?b/ scs /tck? pd0 pdpu pds0 st c?os gene?al pu?pose i/o. registe? enabled pull-up tp? pds0 c?os t?? output tp?b pds0 c?os t?? inve?ted output scs pds0 ifs4 st c?os spi slave sele?t tck? ifs1 st t?? input
rev. 1.00 14 ?a??? ?0? ?01? rev. 1.00 15 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom pad name function opt i/t o/t description pd1/tp?/tp?b/ tp?i/sdo/sck/ scl pd1 pdpu pds0 st c?os gene?al pu?pose i/o. registe? enabled pull-up tp? pds0 c?os t?? output tp?b pds0 c?os t?? inve?ted output tp?i ifs? st t?? input sdo pds0 c?os spi slave sele?t sck pds0 ifs4 st c?os spi se?ial ?lo?k scl pds0 ifs4 st n?os i ? c ?lo?k line pd?/sdi/ sda/tck0 pd? pdpu pds1 st c?os gene?al pu?pose i/o. registe? enabled pull-up sdi pds1 ifs4 st spi data input sda pds1 ifs4 st n?os i ? c data line tck0 ifs1 st t?0 input pd?/tp?/tp?b/ sdo/sck/scl/ tck1 pd? pdpu pds1 st c?os gene?al pu?pose i/o. registe? enabled pull-up tp? pds1 c?os t?? output tp?b pds1 c?os t?? inve?ted output sdo pds1 c?os spi slave sele?t sck pds1 ifs4 st c?os spi se?ial ?lo?k scl pds1 ifs4 st n?os i ? c ?lo?k line tck1 ifs1 st t?1 input pd4/tp?/tp?b/ tp?i pd4 pdpu pds? st c?os gene?al pu?pose i/o. registe? enabled pull-up tp? pds? c?os t?? output tp?b pds? c?os t?? inve?ted output tp?i ifs? st t?? input pd5/tp0/tp0b pd5 pdpu pds? st c?os gene?al pu?pose i/o. registe? enabled pull-up tp0 pds? c?os t?0 output tp0b pds? c?os t?0 inve?ted output pd6/sck/scl pd6 pdpu pds? st c?os gene?al pu?pose i/o. registe? enabled pull-up sck pds? ifs4 st c?os spi se?ial ?lo?k scl pds? ifs4 st n?os i ? c ?lo?k line pd7/ scs pd7 pdpu pds? st c?os gene?al pu?pose i/o. registe? enabled pull-up scs pds? ifs4 st c?os spi slave sele?t pe0/ scsa /int0 pe0 pepu pes0 st c?os gene?al pu?pose i/o. registe? enabled pull-up scsa pes0 ifs5 st c?os spia slave sele ?t int0 integ intc0 ifs0 st exte?nal inte??upt 0
rev. 1.00 16 ?a??? ?0? ?01? rev. 1.00 17 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom pad name function opt i/t o/t description pe1/scka/int1 pe1 pepu pes0 st c?os gene?al pu?pose i/o. registe? enabled pull-up scka pes0 ifs5 st c?os spia se ?ial ?lo?k int1 integ intc0 ifs0 st exte?nal inte??upt 1 pe?/sdia/int? pe? pepu pes1 st c?os gene?al pu?pose i/o. registe? enabled pull-up sdia ifs5 st c?os spi se?ial ?lo?k int? integ intc? ifs0 st exte?nal inte??upt ? pe?/sdoa/tck? pe? pepu pes1 st c?os gene?al pu?pose i/o. registe? enabled pull-up sdoa pes1 st c?os spia se ?ial ?lo?k tck? ifs1 st t?? input pe4/tp1b/ tp1bb/tp1ib pe4 pepu pes? st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1b pes? c?os t?1 b output tp1bb pes? c?os t?1 inve?ted b output tp1ib ifs? st t?1 b input pe5/tp?/tp?b pe5 pepu pes? st c?os gene?al pu?pose i/o. registe? enabled pull-up tp? pes? c?os t?? output tp?b pes? c?os t?? inve?ted output pe6/an8/int0 pe6 pepu pes? st c?os gene?al pu?pose i/o. registe? enabled pull-up an8 pes? an a/d conve?te? analog input int0 integ intc0 ifs0 st exte?nal inte??upt 0 pe7/an9/int1 pe7 pepu pes? st c?os gene?al pu?pose i/o. registe? enabled pull-up an9 pes? an a/d conve?te? analog input int1 integ intc0 ifs0 st exte?nal inte??upt 1 pf0/an10/c1n pf0 pfpu pfs0 st c?os gene?al pu?pose i/o. registe? enabled pull-up an10 pfs0 an a/d conve?te? analog input c1n pfs0 an compa?ato? 1 inte?ting input pf1/an11/c1p pf1 pfpu pfs0 st c?os gene?al pu?pose i/o. registe? enabled pull-up an11 pfs0 an a/d conve?te? analog input c1p pfs0 an compa?ato? 1 non-inte?ting input pf?~pf6 pfn pfpu st c?os gene?al pu?pose i/o. registe? enabled pull-up pg0/c0x pg0 pgpu pgs0 st c?os gene?al pu?pose i/o. registe? enabled pull-up c0x pgs0 c?os compa?ato? 0 output pg1/c1x pg1 pgpu pgs0 st c?os gene?al pu?pose i/o. registe? enabled pull-up c1x pgs0 c?os compa?ato? 1 output
rev. 1.00 16 ?a??? ?0? ?01? rev. 1.00 17 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom pad name function opt i/t o/t description pg?/tck4 pg? pgpu st c?os gene?al pu?pose i/o. registe? enabled pull-up tck4 st t?4 input pg?/tp4/ tp4b/tp4i pg? pgpu pgs1 st c?os gene?al pu?pose i/o. registe? enabled pull-up tp4 pgs1 c?os t?4 output tp4b pgs1 c?os t?4 inve?ted output tp4i ifs? st t?4 input pg4/tp4/ tp4b/tp4i pg4 pgpu pgs? st c?os gene?al pu?pose i/o. registe? enabled pull-up tp4 pgs? c?os t?4 output tp4b pgs? c?os t?4 inve?ted output tp4i ifs? st t?4 input pg5/tck5 pg5 pgpu st c?os gene?al pu?pose i/o. registe? enabled pull-up tck5 st t?5 input pg6/tp5/ tp5b/tp5i pg6 pgpu pgs? st c?os gene?al pu?pose i/o. registe? enabled pull-up tp5 pgs? c?os t?5 output tp5b pgs? c?os t?5 inve?ted output tp5i ifs? st t?5 input pg7/tp5/ tp5b/tp5i pg7 pgpu pgs? st c?os gene?al pu?pose i/o. registe? enabled pull-up tp5 pgs? c?os t?5 output tp5b pgs? c?os t?5 inve?ted output tp5i ifs? st t?5 input ph0/tp0/tp0b/ an0/vref/c0x ph0 phpu phs0 st c?os gene?al pu?pose i/o. registe? enabled pull-up tp0 phs0 c?os t?0 output tp0b phs0 c?os t?0 inve?ted output an0 phs0 an a/d conve?te? analog input vref phs0 an a/d conve?te? ?efe?en?e input c0x phs0 c?os compa?ato? 0 output ph1/tck0/ an?/c0p ph0 phpu phs0 st c?os gene?al pu?pose i/o. registe? enabled pull-up tck0 ifs1 st t?0 input an? phs0 an a/d conve?te? analog input c0p phs0 an compa?ato? 0 non-inve?ting input ph?/ scsa ph? phpu phs1 st c?os gene?al pu?pose i/o. registe? enabled pull-up scsa phs1 ifs5 st c?os spia slave sele ?t ph?/scka ph? phpu phs1 st c?os gene?al pu?pose i/o. registe? enabled pull-up scka phs1 ifs5 st c?os spia se ?ial ?lo?k ph4/sdia ph4 phpu st c?os gene?al pu?pose i/o. registe? enabled pull-up sdia ifs5 st c?os spia se ?ial data input ph5/sdoa ph5 phpu phs? st c?os gene?al pu?pose i/o. registe? enabled pull-up sdoa phs? st c?os spia se ?ial data output vdd vdd pwr positive powe? supply vss vss pwr negative powe? supply. g?ound
rev. 1.00 18 ?a??? ?0? ?01? rev. 1.00 19 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom pad name function opt i/t o/t description vss? vss? pwr i/o pad powe? supply. g?ound note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; co: confguration option st: schmitt trigger input; cmos: cmos output; nmos: nmos output hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator absolute maximum ratings supply voltage ................................................................................................ v ?0.3v to v +6.0v input voltage .................................................................................................. v ? 0.3v to v +0.3v storage temperature .................................................................................................... -50 ? c to 125?c operating temperature .................................................................................................. -40 ? c to 85 ? c total .................................................................................................................................... -80ma ol total ..................................................................................................................................... 80ma total power dissipation ........................................................................................................ 500mw note: these are stress ratings only. stresses exceeding the range specified under "absolute maximum ratings" may cause substantial damage to these devices. functional operation of these devices at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect devices reliability. d.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd1 ope? ating voltage (hxt) f sys =8?hz ?.? 5.5 v f sys =1??hz ?.7 5.5 v f sys =16?hz 4.5 5.5 v v dd? ope? ating voltage (erc) f sys =6?hz ?.? 5.5 v f sys =8?hz ?.7 5.5 v f sys =1??hz 4.5 5.5 v v dd? ope? ating voltage (hirc) f sys =4/8 ?hz ?.? 5.5 v i dd1 ope?ating cu??ent (hxt ? f sys =f h ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =8?hz? adc off? wdt enable 1.0 1.5 ma 5v ?.5 4.0 ma ?v no load? f h =10?hz? adc off? wdt enable 1.? ?.0 ma 5v ?.8 4.5 ma ?v no load? f h =1??hz? adc off? wdt enable 1.5 ?.5 ma 5v ?.5 5.5 ma 5v no load? f h =16?hz? adc off? wdt enable 4.5 7.0 ma
rev. 1.00 18 ?a??? ?0? ?01? rev. 1.00 19 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i dd? ope?ating cu??ent (erc? f sys =f h ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =6?hz? adc off? wdt enable 0.9 1.5 ma 5v ?.0 ?.0 ma ?v no load? f h =8?hz? adc off? wdt enable 1.? ?.0 ma 5v ?.8 4.5 ma 5v no load? f h =1??hz? adc off? wdt enable 4.0 6.0 ma i dd? ope?ating cu??ent (hirc osc? f sys =f h ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =4?hz? adc off? wdt enable 0.7 1.? ma 5v 1.5 ?.5 ma ?v no load? f h =8?hz? adc off? wdt enable 1.? ?.0 ma 5v ?.8 4.5 ma i dd4 ope?ating cu??ent (hxt ? f sys =f l ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =1??hz? f l =f h /?? adc off ? wdt enable 0.9 1.5 ma 5v ?.1 ?.? ma ?v no load? f h =1??hz? f l =f h /4? adc off ? wdt enable 0.6 1.0 ma 5v 1.6 ?.5 ma ?v no load? f h =1??hz? f l =f h /8? adc off ? wdt enable 0.48 0.8 ma 5v 1.? ?.0 ma ?v no load? f h =1??hz? f l =f h /16? adc off ? wdt enable 0.4? 0.7 ma 5v 1.1 1.7 ma ?v no load? f h =1??hz? f l =f h /??? adc off ? wdt enable 0.?8 0.6 ma 5v 1.0 1.5 ma ?v no load? f h =1??hz? f l =f h /64? adc off ? wdt enable 0.?6 0.55 ma 5v 1.0 1.5 ma i dd5 ope?ating cu??ent (lxt ? f sys =f l =f rtc ? f s =f sub =f rtc ) ?v no load? adc off? wdt enable? lxtlp=0? lvd&lvr disable 10 ?0 a 5v ?0 50 a ?v no load? adc off? wdt enable? lxtlp=1? lvd & lvr disable 10 ?0 a 5v ?0 50 a i dd6 ope?ating cu??ent (lirc? f sys =f l =f lirc ? f s =f sub =f lirc ) ?v no load? adc off? wdt enable? lvd&lvr disable 10 ?0 a 5v ?0 50 a i stb1 standby cu??ent (idle1) (hxt ? f sys =f h ? f s =f sub =f rtc o? f lirc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =1??hz 0.6 1.0 ma 5v 1.? ?.0 ma i stb? standby cu??ent (idle0) (hxt ? f sys =off ? f s =f sub =f rtc o? f lirc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =1??hz 1.? ?.0 a 5v ?.? 5.0 a i stb? standby cu??ent (idle0) (erc? f sys =off ? f s =f sub =f rtc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =1??hz 1.? ?.0 a 5v ?.? 5.0 a i stb4 standby cu??ent (idle0) (hirc? f sys =off ? f s =f sub =f lirc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =8?hz 1.? ?.0 a 5v ?.? 5.0 a i stb5 standby cu??ent (idle1) (hxt ? f sys =f l ? f s =f sub =f rtc o? f lirc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =1??hz/64 0.?4 0.6 ma 5v 0.85 1.? ma i stb6 standby cu??ent (idle0) (hxt ? f sys =off ? f s =f sub =f rtc o? f lirc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =1??hz/64 1.? ?.0 a 5v ?.? 5.0 a i stb7 standby cu??ent (idle1) (lxt ? f sys =f l =f rtc ? f s =f sub =f rtc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =??768hz? lxtlp=1 1.9 4.0 a 5v ?.? 7.0 a
rev. 1.00 ?0 ?a??? ?0? ?01? rev. 1.00 ?1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i stb8 standby cu??ent (idle0) (lxt ? f sys =off ? f s =f sub =f rtc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =??768hz? lxtlp=1 1.? ?.0 a 5v ?.? 5.0 a i stb9 standby cu??ent (idle0) (lirc? f sys =off ? f s =f sub =f lirc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =??khz 1.? ?.0 a 5v ?.? 5.0 a i stb10 standby cu??ent (sleep0) (hxt ? f sys =off ? f s =f sub =f rtc o? f lirc ) ?v no load ? system halt ? adc off ? wdt disable ? f sys =1??hz 0.1 1 a 5v 0.? ? a i stb11 standby cu??ent (sleep1) (hxt ? f sys =off ? f s =f sub =f rtc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =1??hz 1.? 5.0 a 5v ?.? 10.0 a i stb1? standby cu??ent (sleep1) (hxt ? f sys =off ? f s =f sub =f lirc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =1??hz 1.? 5.0 a 5v ?.? 10.0 a i stb1? standby cu??ent (sleep0) (lxt ? f sys =off ? f s =f sub =f lirc o? f rtc ) ?v no load ? system halt ? adc off ? wdt disable ? f sys =??768hz 0.1 1 a 5v 0.? ? a i stb14 standby cu??ent (sleep1) (lxt ? f sys =off ? f s =f sub =f rtc ) ?v no load ? system halt ? adc off ? wdt enable ? f sys =??768hz 1.? 5.0 a 5v ?.? 10.0 a i stb15 stanby cu??ent (sleep) (hxt ? f sys =off ? f s =f sub =f rtc o? f lirc ) no load ? system halt ? adc off ? wdt disable ? f sys =1??hz? lvr enable and lvden=1 60 90 a v il1 input low voltage fo ? i/o po?t ex?ept res pin 5 0 1.5 v 0 0.?v dd v v ih1 input hig? voltage fo? i/o po?t ex?ept res pin 5 ?.5 5 v 0.8v dd v dd v v il? input low voltage ( res ) 0 0.4v dd v v ih? input hig? voltage ( res ) 0.9v dd v dd v v sco? v dd /? voltage fo? lcd co?n ?.5v~5.5v no load 0.475 0.500 0.5?5 v dd i ol i/o po?t sink cu??ent ?v v ol =0.1v dd 4 8 ma 5v v ol =0.1v dd 10 ?0 ma i oh i/o po?t sou??e cu??ent ?v v oh =0.9v dd -? -4 ma 5v v oh =0.9v dd -5 -10 ma r ph pull-?ig? resistan?e of i/o po?ts ?v ?0 60 100 k 5v 10 ?0 50 k
rev. 1.00 ?0 ?a??? ?0? ?01? rev. 1.00 ?1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom a.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd condition f sys1 system ?lo?k (hxt) ?.?~5.5v 0.4 8 ?hz ?.7~5.5v 0.4 1? ?hz 4.5~5.5v 0.4 16 ?hz f sys? system ?lo?k (erc) 5v ta= ?5c? exte?nal r erc =1?0k -?% 8 +?% ?hz f sys? system ?lo?k (hirc) 5v ta= ?5c -?% 8 +?% ?hz f sys4 system clo?k (lxt) ??768 hz f sys5 system clo?k (lirc) 5v ta= ?5c -?% ?? +?% khz t ti?er tckn and time? ?aptu?e input pulse widt? 0.? s t res exte?nal reset low pulse widt? 10 s t int inte??upt pulse widt? 10 s t sst system sta? t-up time? pe?iod (wake-up f ? om halt ? f sys off at halt state ? slow ?ode : no?mal ?ode? no?mal ?ode : slow ?ode) f sys =hxt o ? lxt (slow ?ode : no?mal ?ode(hxt)? no?mal ?ode : slow ?ode(lxt) ) 10?4 t sys f sys =hxt o ? lxt (wake-up f ? om halt ? f sys off at halt state) 10?4 t sys f sys =erc o? hirc 16 t sys f sys =lirc ? t sys system sta? t-up time? pe?iod (wake-up f ? om halt ? f sys on at halt state) ? t sys system sta? t-up time? pe?iod (reset) 10?4 t sys t rstd system reset delay time (powe? on reset? lvr ?eset? lvrc softwa?e ?eset? wdtc softwa?e ?eset) ?5 50 100 ms system reset delay time ( res ?eset? wdt no?mal ?eset) 8.? 16.7 ??.? ms t eerd eepro? read time 1 ? 4 t sys t eewr eepro? w ? ite timet 1 ? 4 ms note: t sys i sys
rev. 1.00 ?? ?a??? ?0? ?01? rev. 1.00 ?? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom a/d converter characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd condition v adi a/d conve?te? input voltage 0 v ref v v ref a/d conve?te? refe?en? e voltage ? av dd v dnl diffe ?ential non-linea?ity 5v t adck =0.5s -? +? lsb inl integ?al non-linea?ity 5v t adck =0.5s -4 +4 lsb i adc additional powe? consumption if a/d conve?te? is used ?v no load (t adck =0.5s ) 1.0 ?.0 ma 5v no load (t adck =0.5s ) 1.5 ?.0 ma t adck a/d conve?te? clo?k pe?iod 0.5 100 s t adc a/d conve ? sion time (in? lude sample and hold time) 1? bit a/d conve?te? 16 t adck t ads a/d conve?te? sampling time 4 t adck t on?st a/d conve?te? on-to-sta? t time ? s lvd & lvr electrical characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr1 low voltage reset voltage lvr enable ? ?.1v option -5% ?.1 +5% v v lvr ? lvr enable ? ?.55v option ?.55 v lvr ? lvr enable ? ?.15v option ?.15 v lvr4 lvr enable ? ?.8v option ?.8 v lvd1 low voltage dete ?to? voltage lvden=1 ? v lvd =?.0v -5% ?.0 +5% v v lvd ? lvden=1 ? v lvd =?.?v ?.? v v lvd ? lvden=1 ? v lvd =?.4v ?.4 v v lvd4 lvden=1 ? v lvd =?.7v ?.7 v v lvd5 lvden=1 ? v lvd =?.0v ?.0 v v lvd6 lvden=1 ? v lvd =?.?v ?.? v v lvd7 lvden=1 ? v lvd =?.6v ?.6 v v lvd8 lvden=1 ? v lvd =4.0v 4.0 v v bg bandgap ?efe?en?e wit? buffe? voltage -?% 1.?5 +?% v i bg additional powe? consumption if bandgap ?efe?en?e wit? buffe? is used ?00 ?00 a i lvr additional powe ? consumption if lvr is used ?v lvr disablelvr enable ?0 45 a 5v 60 90 a i lvd additional powe ? consumption if lvd is used ?v lvd disablelvd enable (lvr disable) 40 60 a 5v 75 115 a ?v lvd disablelvd enable (lvr enable) ?0 45 a 5v 60 90 a t bgs v bg tu?n on stable time 10 ms t lvr low voltage widt ? to reset 1?0 480 s t lvd low voltage widt ? to inte??upt ?0 45 90 s t lvds lvdo stable time for lvr enable, lvd offon 15 s for lvr disable, lvd offon 15 s t sreset softwa?e reset widt? to reset 45 90 1?0 s
rev. 1.00 ?? ?a??? ?0? ?01? rev. 1.00 ?? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom comparator electrical characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd condition v c?p compa?ato? ope?ating voltage ?.? 5.5 v i c?p compa?ato? ope?ating ?u??ent ?v 50 75 a 5v 85 1?0 a v c?pos compa?ato? input offset voltage -10 +10 mv v hys hyste?esis widt? ?0 40 60 mv v c? compa?ato? ?ommon mode voltage ?ange v ss v dd -1.4v v a ol compa?ato? open loop gain 60 80 db t pd compa?ato? ?esponse time ?v wit? 100mv ove?d?ive (note) ?00 400 ns 5v note: 0hdvxuhg zlwk frpsdudwru rh lsxw sl dw 0 dd zkloh wkh rwkhu sl lsxw wudvlwlr iurp ss wr 0 pruiurp dd wr 0 p power on reset electrical characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd condition v por v dd sta? t voltage to ensu?e powe?-on reset 100 mv rr vdd v dd rise rate to ensu?e powe?-on reset 0.0?5 v/ms t por ? inimum time fo? v dd to ?emain at v por to ensu?e powe?-on reset 1 ms
rev. 1.00 ?4 ?a??? ?0? ?01? rev. 1.00 ?5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility. this makes these devices suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, lxt, hirc, lirc or erc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? system clocking and pipelining
rev. 1.00 ?4 ?a??? ?0? ?01? rev. 1.00 ?5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter porgram counter high byte porgram counter low byte HT66F60A pc1?~pc8 pcl7~pcl0 ht66f70a pc14~pc8 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.00 ?6 ?a??? ?0? ?01? rev. 1.00 ?7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa, ladd, laddm, ladc, ladcm, lsub, lsubm, lsbc, lsbcm, ldaa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla, land, lor, lxor, landm, lorm, lxorm, lcpl, lcpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc, lrra, lrr, lrrca, lrrc, lrla, lrl, lrlca, lrlc ? increment and decrement: inca, inc, deca, dec, linca, linc, ldeca, ldec ? branch decision: jmp, call, ret, reti, sz, sza, snz, siz, sdz, siza, sdza, lsz, lsza, lsnz, lsiz, lsdz, lsiza, lsdza
rev. 1.00 ?6 ?a??? ?0? ?01? rev. 1.00 ?7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom flash program memory the program memory is the location where the user code or program is stored. for these devices series the program memory are flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, these flash devices offer users the fexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of 16k16 bits to 32k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries information. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. device capacity banks HT66F60A 16k 16 0~1 ht66f70a ??k 16 0~? the series of devices has its program memory divided into two or four banks, bank 0~bank 1 or bank 0~bank 3 respectively. the required bank is selected using bit 0 or bit 0~1 of the bp register dependent upon which device is selected. 0000h 0004h 00?8h reset inte??upt ve?to? 16 bits HT66F60A 1fffh bank 1 ?000h ?fffh reset inte??upt ve?to? 16 bits ht66f70a bank 1 bank ? bank ? 4000h 5fffh 6000h 7fffh program memory structure
rev. 1.00 ?8 ?a??? ?0? ?01? rev. 1.00 ?9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 0000h is reserved for use by these devices reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the tabrd[m] or tabrdl[m] instructions respectively when the memory [m] is located in current page. if the memory [m] is located in other pages, the data can be retrieved from the program memory using the ltabrd[m] or ltabrdl[m] instructions respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. the accompanying diagram illustrates the addressing data fow of the look-up table.

rev. 1.00 ?8 ?a??? ?0? ?01? rev. 1.00 ?9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom table program example the accompanying example shows how the table pointer and table data is defned and retrieved from the device. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 3f00h which refers to the start address of the last page within the 16k program memory of the HT66F60A device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 3f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example: tempreg1 db ? ; temporary register #1 in current page tempreg2 db ? ; temporary register #2 in current page : : mov a,06h ; initialise low byte table pointer - note that this address ; is referenced mov tblp, a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempreg1 ; data at program memory address 3f06h transferred to tempreg1 ; and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at program memory address 3f05h transferred to tempreg2 ; and tblh. in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 while the value 00h ; will be transferred to the high byte register tblh : : org 3f00h ; sets initial address of last page dc 000ah, 000bh, 000ch, 000dh, 000eh, 000fh, 001ah, 001bh : :
rev. 1.00 ?0 ?a??? ?0? ?01? rev. 1.00 ?1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. holtek writer pins mcu programming pins pin description icpda pa0 p?og?amming se?ial data icpck pa ? p?og?amming clo?k vdd vdd powe? supply vss vss g?ound the program memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, the user must take care of the icpda and icpck pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins.
note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf.
rev. 1.00 ?0 ?a??? ?0? ?01? rev. 1.00 ?1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom on-chip debug support C ocds there is an ev chip named ht66v70a which is used to emulate the ht66fx0a series of devices. the ht66v70a device also provides the on-chip debug function to debug the ht66fx0a series of devices during development process. the devices, ht66fx0a and ht66v70a, are almost functional compatible except the on-chip debug function and package types. users can use the ht66v70a device to emulate the ht66fx0a series of devices behaviors by connecting the ocdsda and ocdsck pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ht66v70a ev chip for debugging, the corresponding pin functions shared with the ocdsda and ocdsck pins in the ht66fx0a series of devices will have no effect in the ht66v70a ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp. for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on-c?ip debug suppo?t data/add?ess input/output ocdsck ocdsck on-c?ip debug suppo?t clo?k input vdd vdd powe? supply gnd vss g?ound in application programming C iap this device offers iap function to update data or application program to flash rom. users can defne any rom location for iap, but there are some features which user must notice in using iap function. ? erase page: 64 words/page ? writing: 64 words/time ? reading: 1 word/time in application programming control register the address register, farl and farh, and the data registers, fd0l/fd0h, fd1l/fd1h, fd2l/fd2h and fd3l/fd3h, located in data memory section0, together with the control registersr, fc0, fc1 and fc2, located in data memory section1 are the corresponding flash access registers for iap. as indirect addressing is the only way to access the fc0, fc1 and fc2 registers, all read and write operations to the registers must be performed using the indirect addressing register, iar1, and the memory pointer pair, mp1l and mp1h. because the fc0, fc1 and fc2 control registers are located at the address of 43h~45h in data memory section1, the desired value ranged from 43h to 45h must frst be written into the mp1l memory pointer low byte and the value 01h must also be written into the mp1h memory pointer high byte.
rev. 1.00 ?? ?a??? ?0? ?01? rev. 1.00 ?? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? fc0 register bit 7 6 5 4 3 2 1 0 name cfwen f?od? f?od1 f?od0 fwpen fwt frden frd r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 1 1 0 0 0 0 %lw cfwen: odvk0hpru :ulwh hdeohfrwuro odvkphpruzulwhixfwlrlvglvdeohg odvkphpruzulwhixfwlrkdvehhvxffhvvixoohdeohg :kh wklv elw lv fohduhg wr e dssolfdwlr surudp wkh odvk phpru zulwh ixfwlr lv glvdeohg 1rwh wkdw zulwl d lwr wklv elw uhvxowv l r dfwlr 7klv elw lv xvhg wr lglfdwh wkdw wkh odvk phpru zulwh ixfwlr vwdwxv :kh wklv elw lv vhw wr e kdugzduh lw phdv wkdw wkh odvk phpru zulwh ixfwlr lv hdeohg vxffhvvixoo 2wkhuzlvhwkhodvkphpruzulwhixfwlrlvglvdeohgdvwkhelwfrwhwlv]hur lw fmod2~fmod0: 0rghvhohfwlr :ulwh surudpphpru 3dhhudvhsurudpphpru 5hvhuyhg 5hdgsurudpphpru 5hvhuyhg :1prghodvkphpru :ulwh ixfwlrdeohprgh 5hvhuyhg lw fwpen: odvkphpruzulwhsurfhgxuhhdeohfrwuro lvdeoh deoh :kh wklv elw lv vhw wr dg wkh 02 hog lv vhw wr wkh ,3 frwuroohu zloo h[hfxwh wkh odvk phpru zulwh ixfwlr hdeoh surfhgxuh 2fh wkh odvk phpru zulwh ixfwlr lv vxffhvvixoo hdeohg lw lv rw hfhvvdu wr vhw wkh :31 elw d pruh lw fwt: odvk520zulwhfrwuroelw rrwllwldwhodvkphpruzulwhruodvkphpru :ulwh surfhvvlvfrpsohwhg ,lwldwhodvkphpruzulwhsurfhvv 7klv elw lv vhw e vriwzduh dg fohduhg e kdugzduh zkh wkh odvk phpru zulwh surfhvvlvfrpsohwhg lw frden: odvkphpruuhdghdeohelw odvkphpruuhdgglvdeoh odvkphpruuhdghdeoh lw frd: odvkphpruuhdgfrwuroelw rrwllwldwhodvkphpruuhdgruodvkphpruuhdgsurfhvvlvfrpsohwhg ,lwldwhodvkphpruuhdgsurfhvv 7klv elw lv vhw e vriwzduh dg fohduhg e kdugzduh zkh wkh odvk phpru uhdg surfhvvlvfrpsohwhg
rev. 1.00 ?? ?a??? ?0? ?01? rev. 1.00 ?? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? fc1 register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lwa 55h: zkrohfklsuhvhw :kh xvhu zulwhv wr wklv uhlvwhu lw zloo hhudwh d uhvhw vldo wr uhvhw zkroh fkls ? fc2 register bit 7 6 5 4 3 2 1 0 name clwb r/w r/w por 0 %lw a 8qlpsohphqwhguhdgdv %lw clwb: odvk0hpru :ulwh exiihufohdufrwuro rrwllwldwh :luwh xiihuohduru :luwh xiihuohdusurfhvvlvfrpsohwhg ,lwldwh :luwh xiihuohdusurfhvv 7klv elw lv vhw e vriwzduh dg fohduhg e kdugzduh zkh wkh :luwh xiihu ohdu surfhvvlvfrpsohwhg ? farl register bit 7 6 5 4 3 2 1 0 name a7 a6 a5 a4 a? a? a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a )odvk0hpru gguhvv> ? farh register bit 7 6 5 4 3 2 1 0 name a14 a1? a1? a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 %lw 8qlpsohphqwhguhdgdv %lw a )odvk0hpru gguhvv> ? fd0l register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7khuvw)odvk0hprugdwd> ? fd0h register bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7khuvw)odvk0hprugdwd>
rev. 1.00 ?4 ?a??? ?0? ?01? rev. 1.00 ?5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? fd1l register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7khvhfrqg)odvk0hprugdwd> ? fd1h register bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7khvhfrqg)odvk0hprugdwd> ? fd2l register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7khwklug)odvk0hprugdwd> ? fd2h register bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7khwklug)odvk0hprugdwd> ? fd3l register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7khirxuwk)odvk0hprugdwd> ? fd3h register bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7khirxuwk)odvk0hprugdwd>
rev. 1.00 ?4 ?a??? ?0? ?01? rev. 1.00 ?5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom flash memory write function enable procedure in order to allow users to change the flash memory data through the iap control registers, users must frst enable the flash memory write operation by the following procedurce: ? write 110 into the fmod2~fmod0 bits to select the fwen mode. ? set the fwpen bit to 1. the step 1 and step 2 can be executed simultaneously. ? the pattern data with a sequence of 00h, 04h, 0dh, 09h, c3h and 40h must be written into the fd1l, fd1h, fd2l, fd2h, fd3l and fd3h registers respectively. ? a counter with a time-out period of 300s will be activated to allow users writing the correct pattern data into the fd1l/fd1h~fd3l/fd3h register pairs. the counter clock is derived from lirc oscillator. ? if the counter overfows or the pattern data is incorrect, the flash memory write operation will not be enabled and users must again repeat the above procedure. then the fwpen bit will automatically be cleared to 0 by hardware. ? if the pattern data is correct before the counter overfows, the flash memory write operation will be enabled and the fpwen bit will automatically be cleared to 0 by hardware. the cfwen bit will also be set to 1 by hardware to indicate that the flash memory write operation is successfully enabled. ? once the flash memory write operation is enabled, the user can change the flash rom data through the flash control register. ? to disable the flash mermoy write operation, the user can clear the cfwen bit to 0. flas? ?emo?y w?ite fun?tion enable p?o?edu?e set f?od [?:0] =110 & fwpen=1 :sele?t fwen mode & sta?t flas? w?ite ha?dwa?e a?tivate a ?ounte? w?tie t?e following patte?n to flas? data ?egiste?s fd1l= 00? ? fd1h = 04? fd?l= 0d? ? fd?h = 09? fd?l= c?? ? fd?h = 40? is patte?n is ?o??e?t ? is ?ounte? ove?flow ? fwpen=0 ? yes no no yes su??ess end no yes failed fwpen=0 & cfwen=0 cfwen = 1 flash memory write function enable procedure
rev. 1.00 ?6 ?a??? ?0? ?01? rev. 1.00 ?7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom w?ite flas? ?emo?y flas? ?emo?y w?ite fun?tion enable p?o?edu?e set fwt=1 fwt=0 ? yes no set page e?ase add?ess: farh/farl set f?od [?:0 ]=001 & fwt=1 sele?t page e?ase mode & initiate w?ite ope?ation fwt=0 ? yes no end w?ite finis? ? yes no clea? cfwen=0 set f?od [?:0]=000 sele?t w?ite flas? ?ode set page e?ase add?ess: farh/farl w?ite data to data ?egiste?: fd0l/fd0h page data w?ite finis? ? yes no write flash memory procedure
rev. 1.00 ?6 ?a??? ?0? ?01? rev. 1.00 ?7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom erase page farh farl[7:6] note 0 0000 0000 00 farl [5:0]: dont ?a?e 1 0000 0000 01 ? 0000 0000 10 ? 0000 0000 11 4 0000 0001 00 5 0000 0001 01 6 0000 0001 10 7 0000 0001 11 8 0000 0010 00 9 0000 0010 01 : : : : : : ?5? 0011 1111 00 ?5? 0011 1111 01 ?54 0011 1111 10 ?55 0011 1111 11 : : : : : : 508 0111 1111 00 509 0111 1111 01 510 0111 1111 10 511 0111 1111 11 note: there are 256 iap erase pages in the HT66F60A device while there are 512 iap erase pages in the ht66f70a device.
rev. 1.00 ?8 ?a??? ?0? ?01? rev. 1.00 ?9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom read flas? ?emo?y clea? fwen bit end read finis? ? yes no set f?od [?: 0]=011 & frden=1 set flas? add?ess ?egiste?s fah=xx?? fal =xx? frd=0 ? yes no read data value: fd0l=xx?? fd0h= xx? set frd=1 read flash memory procedure note: when the fwt or frd bit is set to 1, the mcu is stopped.
rev. 1.00 ?8 ?a??? ?0? ?01? rev. 1.00 ?9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom data memory the data memory is an 8-bit wide ram internal memory and is the location where temporary information is stored. divided into two types, the frst of data memory is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. structure the data memory is divided into several sections, all of which are implemented in 8-bit wide memory. each of the data memory sections is categorized into two types, the special purpose data memory and the general purpose data memory. the start address of the special purpose data memory for all devices is the address 00h while the start address of the general purpose data memory is the address 80h. the special purpose registers which are addressed from 00h to 3fh in data memory are common to all sections and are accessible in all sections. however, the special purpose registers located in the section 1 can only be accessed with the address from 40h to ffh. device capacity sections HT66F60A gene?al pu?pose: 10?48 0: 80h~ffh 1: 80h~ffh : : 7: 80h~ffh ht66f70a gene?al pu?pose: ?0488 0: 80h~ffh 1: 80h~ffh : : 15: 80h~ffh
rev. 1.00 40 ?a??? ?0? ?01? rev. 1.00 41 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom spe?ial pu?pose data ?emo?y gene?al pu?pose data ?emo?y 00h 7fh 80h ffh se?tion 0 40h in se?tion 1 se?tion 0 se?tion 1 se?tion ? se?tion n ffh in se?tion 1 n=7 fo? HT66F60A; n=15 fo? ht66f70a data memory structure general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user programing for both reading and writing operations. by using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h.
rev. 1.00 40 ?a??? ?0? ?01? rev. 1.00 41 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom 00h iar0 01h ?p0 0?h iar1 0?h ?p1l 04h 05h acc 06h pcl 07h tblp 08h tblh 09h tbhp 0ah status 0bh s?od 0ch lvdc 0dh integ 0eh wdtc 0fh tbc0 10h intc0 11h intc1 1?h 19h papu 18h pawu 1bh 1ah 1dh 1ch 1fh pa pac 1eh HT66F60A spe?ial pu?pose data ?emo?y bp 1?h 14h ?fi0 15h ?fi1 16h 17h ?fi? se?tion 0~7 s?od? lvrc unused pbpu pb pbc pcpu pc pcc pdpu pd pdc pepu pe pec pfpu pf pfc pgpu pg pgc phpu ph phc ?0h ?1h ??h ?9h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ??h ?4h ?5h ?6h ?7h ?0h ?1h ??h ?9h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ??h ?4h ?5h ?6h ?7h t?4c0 t?4c1 t?4dl t?4dh t?4al t?4ah 40h eec 41h eea 4?h eed 4?h t??c0 47h t??c1 48h t?1c? 49h t??dl 4ah t??dh 4bh t??al 4ch t??ah 4dh t?1bl 4eh t?1 bh 4fh 50h 51h 5?h 58h 5?h 54h 55h 56h 57h se?tion 0? ? ~7 se?tion 1 unused t?1c0 t?1c1 t?1dl t?1dh t?1al t?1ah t??rp 60h 61h ?p1h iar? ?p?l ?p?h unused unused unused unused unused unused unused intc? intc? ?fi? ?fi4 s?od1 44h 45h 46h fc0 fc1 fc? ifs0 ifs1 ifs? ifs? ifs4 ifs5 59h 5ah 5bh 5ch 5dh 5eh 5fh t??c0 t??c1 t??dl t??dh t??al t??ah t?0c0 t?0c1 t?0dl t?0dh t?0al t?0ah 6?h 6?h 64h 65h 66h 67h 68h 69h psc0 tbc1 psc1 adcr0 adcr1 6ah 6bh 6dh 6ch 6eh 6fh adrl adrh si?c0 si?c1 si?d si?c?/si?a cp1c cp0c i?ctoc spiac0 spiac1 spiad 70h 71h 7?h 7?h 74h 75h 76h 77h 78h 79h 7ah 7bh 7dh 7ch 7eh 7fh farl farh fd0l fd0h fd1l fd1h fd?l fd?h fd?l fd?h tbc? sco?c t?4rp t?5c0 t?5c1 t?5dl t?5dh t?5al t?5ah t?5rp pas0 pas1 pas? pas? pbs? pbs? pcs0 pcs1 pcs? pcs? pds0 pds1 pds? pds? pes0 pes1 pes? pes? pfs0 pgs0 pgs1 pgs? pgs? phs0 phs1 phs? : unused? ?ead as 00h unused unused unused unused unused unused unused unused unused unused unused unused unused unused unused unused unused 00h iar0 01h ?p0 0?h iar1 0?h ?p1l 04h 05h acc 06h pcl 07h tblp 08h tblh 09h tbhp 0ah status 0bh s?od 0ch lvdc 0dh integ 0eh wdtc 0fh tbc0 10h intc0 11h intc1 1?h 19h papu 18h pawu 1bh 1ah 1dh 1ch 1fh pa pac 1eh ht66f70a spe?ial pu?pose data ?emo?y bp 1?h 14h ?fi0 15h ?fi1 16h 17h ?fi? se?tion 0~15 s?od? lvrc unused pbpu pb pbc pcpu pc pcc pdpu pd pdc pepu pe pec pfpu pf pfc pgpu pg pgc phpu ph phc ?0h ?1h ??h ?9h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ??h ?4h ?5h ?6h ?7h ?0h ?1h ??h ?9h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ??h ?4h ?5h ?6h ?7h t?4c0 t?4c1 t?4dl t?4dh t?4al t?4ah 40h eec 41h eea 4?h eed 4?h t??c0 47h t??c1 48h t?1c? 49h t??dl 4ah t??dh 4bh t??al 4ch t??ah 4dh t?1bl 4eh t?1 bh 4fh 50h 51h 5?h 58h 5?h 54h 55h 56h 57h se?tion 0? ? ~15 se?tion 1 unused t?1c0 t?1c1 t?1dl t?1dh t?1al t?1ah t??rp 60h 61h ?p1h iar? ?p?l ?p?h unused unused unused unused unused unused unused intc? intc? ?fi? ?fi4 s?od1 44h 45h 46h fc0 fc1 fc? ifs0 ifs1 ifs? ifs? ifs4 ifs5 59h 5ah 5bh 5ch 5dh 5eh 5fh t??c0 t??c1 t??dl t??dh t??al t??ah t?0c0 t?0c1 t?0dl t?0dh t?0al t?0ah 6?h 6?h 64h 65h 66h 67h 68h 69h psc0 tbc1 psc1 adcr0 adcr1 6ah 6bh 6dh 6ch 6eh 6fh adrl adrh si?c0 si?c1 si?d si?c?/si?a cp1c cp0c i?ctoc spiac0 spiac1 spiad 70h 71h 7?h 7?h 74h 75h 76h 77h 78h 79h 7ah 7bh 7dh 7ch 7eh 7fh farl farh fd0l fd0h fd1l fd1h fd?l fd?h fd?l fd?h tbc? sco?c t?4rp t?5c0 t?5c1 t?5dl t?5dh t?5al t?5ah t?5rp pas0 pas1 pas? pas? pbs? pbs? pcs0 pcs1 pcs? pcs? pds0 pds1 pds? pds? pes0 pes1 pes? pes? pfs0 pgs0 pgs1 pgs? pgs? phs0 phs1 phs? : unused? ?ead as 00h unused unused unused unused unused unused unused unused unused unused unused unused unused unused unused unused unused HT66F60A special purpose data memory ht66f70a special purpose data memory
rev. 1.00 4? ?a??? ?0? ?01? rev. 1.00 4? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0, iar1 and iar2, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0, iar1 and iar2 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0, mp1l/mp1h or mp2l/mp2h. acting as a pair, iar0 and mp0 can together access data only from section 0 while the iar1 register together with mp1l/mp1h register pair and iar2 register together with mp2l/mp2h register pair can access data from any data memory section. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 five memory pointers, known as mp0, mp1l, mp1h, mp2l and mp2h, are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from section 0, while mp1l/mp1h together with iar1 and mp2l/mp2h together with iar2 are used to access data from all data sections according to the corresponding mp1h or mp2h register. direct addressing can be used in all data sections using the corresponding instruction which can address all available data memory space. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc ram addresses.
rev. 1.00 4? ?a??? ?0? ?01? rev. 1.00 4? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom bank pointer C bp depending upon which device is used, the program memory is divided into several banks. selecting the required program memory area is achieved using the bank pointer. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing. as both the program memory and data memory share the same bank pointer register, care must be taken during programming. device bit 7 6 5 4 3 2 1 0 HT66F60A bp0 ht66f70a bp1 bp0 bp register list bp register C HT66F60A bit 7 6 5 4 3 2 1 0 name bp0 r/w r/w por 0 bit 7~1 unimplemented, read as "0" bit 0 bp0: program memory bank point 0: bank 0 1: bank 1 bp register C ht66f70a bit 7 6 5 4 3 2 1 0 name bp1 bp0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 bp1~bp0: program memory bank point 00: bank 0 01: bank 1 10: bank 2 11: bank 3 accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted.
rev. 1.00 44 ?a??? ?0? ?01? rev. 1.00 45 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer and indicates the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status thi s 8-bit register c ontains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), sc flag, cz flag, power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the "clr wdt" or "halt" instruction. the pdf fag is affected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac, c, sc and cz fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. ? sc is the result of the xor operation which is performed by the ov fag and the msb of the current instruction operation result. ? cz is the operational result of different fags for different instuctions. refer to register defnitions for more details. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to co rrectly save it .
rev. 1.00 44 ?a??? ?0? ?01? rev. 1.00 45 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom status register bit 7 6 5 4 3 2 1 0 name sc cz to pdf ov z ac c r/w r r r r r/w r/w r/w r/w por x x 0 0 x x x x x: unknown bit 7 sc: the result of the xor operation which is performed by the ov fag and the msb of the instruction operation result. bit 6 cz: the the operational result of different fags for different instuctions. for sub/subm/lsub/lsubm instructions, the cz flag is equal to the z flag. for sbc/ sbcm/ lsbc/ lsbcm instructions, the cz fag is the and operation result which is performed by the previous operation cz fag and current operation zero fag. for other instructions, the cz fag willl not be affected. bit 5 to: watchdog time-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf: power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.00 46 ?a??? ?0? ?01? rev. 1.00 47 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom eeprom data memory these devices contain an area of internal eeprom data memory. eeprom, which stands for electrically erasable programmable read only memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. device capacity address HT66F60A 1?88 00h~7fh ht66f70a eeprom data memory structure the eeprom data memory capacity is 1288 bits for this series of devices. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read andwrite operations to the eeprom are carried out in single byte operations using an address and data register in section 0 and a single control register in section 1. eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in section 0, they can be directly accessed in the same was as any other special function register. the eec register however, being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in section 1, the mp1l memory pointer low byte must frst be set to the value 40h and the mp1h memory pointer high byte set to the value 01h before any operations on the eec register are executed. eea register bit 7 6 5 4 3 2 1 0 name eea6 eea5 eea4 eea? eea? eea1 eea0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x: unknown bit 7 unimplemented, read as "0" bit 6~0 eea6~eea0: data eeprom address bit 6~bit 0 eed register bit 7 6 5 4 3 2 1 0 name eed7 eed6 eed5 eed4 eed? eed? eed1 eed0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown bit 7~0 eed7~eed0: data eeprom data bit 7~bit 0
rev. 1.00 46 ?a??? ?0? ?01? rev. 1.00 47 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren: data eeprom write operation enable 0: disable 1: enable this is the data eeprom write operation enable bit which must be set high before datat eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr: data eeprom write control 0: write cycle has fnished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no effect if the wren bit has not frst been set high. bit 1 rden: data eeprom read operation enable 0: disable 1: enable this is the data eeprom read operation enable bit which must be set high before datat eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd: data eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden bit has not frst been set high. note: the wren, wr, rden and rd bits can not be set to 1 at the same time in one instruction. the wr and rd bits can not be set to 1 at the same time. reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading.
rev. 1.00 48 ?a??? ?0? ?01? rev. 1.00 49 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom writing data to the eeprom the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register. to write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should also frst be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the memory pointer pairs, mp1l/mp1h and mp2l/mp2h, will be reset to zero, which means that data memory section 0 will be selected. as the eeprom control register is located in section 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section. programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the write enable bit is normally cleared to zero when not writing. also the memory pointer high byte, mp1h or mp2h, could be normally cleared to zero as this would inhibit access to data memory section 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly. the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts.
rev. 1.00 48 ?a??? ?0? ?01? rev. 1.00 49 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom programming examples reading data from the eeprom C polling mothod mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer mp1l mov mp1l, a ; mp1 points to eec register mov a, 01h ; setup memory pointer mp1h mov mp1h, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr mp1h mov a, eed ; move read data to register mov read_data, a writing data to the eeprom C polling mothod clr emi mov a, eeprom_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer mp1l mov mp1l, a ; mp1 points to eec register mov a, 01h ; setup memory pointer mp1h mov mp1h, a set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit - executed immediately ; after set wren bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr mp1h
rev. 1.00 50 ?a??? ?0? ?01? rev. 1.00 51 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. external oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, these devices have the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name frequency pins exte?nal c?ystal hxt 400khz~16?hz osc1/osc? exte?nal rc erc 400khz~16?hz osc1 inte?nal hig? speed rc hirc 8?hz exte?nal low speed c?ystal lxt ??.768khz xt1/xt? inte?nal low speed rc lirc ??khz oscillator types system clock confgurations there are fve methods of generating the system clock, three high speed oscillators and two low speed oscillators. the high speed oscillators are is the external crystal/ceramic oscillator, external rc network oscillator and the internal 8mhz rc oscillator. the two low speed oscillators are the internal 32khz rc oscillator and the external 32.768khz crystal oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2~cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator.
rev. 1.00 50 ?a??? ?0? ?01? rev. 1.00 51 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom hxt hirc p?es?ale? f h lirc lxt hig? speed os?illation (hosc) low speed os?illation (losc) f h /? f h /16 f h /64 f h /8 f h /4 f h /?? hig? speed os?illation configu?ation option low speed os?illation configu?ation option cks[?:0]? hlclk f sys fast wake-up f?om sleep ?ode o? idle ?ode cont?ol (fo? hxt only) f sys /4 f sub f tb wdt time base clks0[1:0] erc f sub f sub f sys f h p?es?ale? f p clks1[1:0] p?es?ale? pe?ip?e?al clo?k output (pck) tb? [?:0] tb0 [?:0] tb1 [?:0] f sys /4 f sub f sys f h external crystal/ceramic oscillator C hxt the external crystal/ceramic system oscillator is one of the high frequency oscillator choices, which is selected via configuration option. for most crystal oscillator configurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer's specifcation.

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crystal/resonator oscillator C hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 1??hz 0pf 0pf 8?hz 0pf 0pf 4?hz 0pf 0pf 1?hz 100pf 100pf note: c1 and c? values a?e fo? guidan? e only. crystal recommended capacitor values
rev. 1.00 5? ?a??? ?0? ?01? rev. 1.00 5? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom external rc oscillator C erc using the erc oscillator only requires that a resistor, with a value between 56k and 2.4m , is connected between osc1 and vdd, and a capacitor is connected between osc1 and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation frequency; the external capacitor has no infuence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a resistance/frequency reference point, it can be noted that with an external 120k resistor connected and with a 5v voltage power supply and temperature of 25 c degrees, the oscillator will have a frequency of 8mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pb1, leaving pin pb2 free for use as a normal i/o pin. external rc oscillator C erc internal high speed rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 8mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 c degrees, the fxed oscillation frequency of 8mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pb1 and pb2 are free for use as normal i/o pins.
rev. 1.00 5? ?a??? ?0? ?01? rev. 1.00 5? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specification. the external parallel feedback resistor, rp, is required. some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins.
? ?? ?? ? - - external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 ??.768khz 10pf 10pf note: 1. c1 and c? values a?e fo? guidan? e only. ?. r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values
rev. 1.00 54 ?a??? ?0? ?01? rev. 1.00 55 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the smod2 register. ? smod2 register bit 7 6 5 4 3 2 1 0 name lxtlp r/w r/w por 0 bit 7~1 unimplemented, read as "0" bit 0 lxplp: lxt low power control 0: quick start mode 1: low power mode after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low-power mode. internal low speed oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 3%. supplementary oscillators the low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other devices functions. these are the watchdog timer and the time base interrupts.
rev. 1.00 54 ?a??? ?0? ?01? rev. 1.00 55 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clock the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency, f h , or low frequency, f sub , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from an hxt, erc or hirc oscillator, selected via a confguration option. the low speed system clock source can be sourced from the clock, f sub . if f sub is selected then it can be sourced by either the lxt or lirc oscillators, selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. the f sub clock is also used to provide the clock source for time base and watchdog timer functions. hxt hirc p?es?ale? f h lirc lxt hig? speed os?illation (hosc) low speed os?illation (losc) f h /? f h /16 f h /64 f h /8 f h /4 f h /?? hig? speed os?illation configu?ation option low speed os?illation configu?ation option cks[?:0]? hlclk f sys fast wake-up f?om sleep ?ode o? idle ?ode cont?ol (fo? hxt only) f sys /4 f sub f tp wdt time base clks0[1:0] erc f sub f sub f sys f h p?es?ale? system clock confgurations when the system clock source f sys is switched to f sub from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use.
rev. 1.00 56 ?a??? ?0? ?01? rev. 1.00 57 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom system operation modes there are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operating mode description cpu f sys f sub nor? al ?ode on f h ~f h /64 on slow ?ode on f sub on idle0 ?ode off off on idle1 ?ode off on on sleep0 ?ode off off off sleep1 ?ode off off on normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt, erc or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep0 mode is entered when an halt instruction is executed and the idlen bit in the smod register is low. in the sleep0 mode the cpu will be stopped and the f sub clock will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to 0. if the lvden is set to 1, it wont enter the sleep0 mode. sleep1 mode the sleep1 mode is entered when an halt instruction is executed and the idlen bit in the smod register is low. in the sleep1 mode the cpu will be stopped. however the f sub will continue to operate if the lvden is 1 or the watchdog timer function is enabled. idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer and tms. in the idle0 mode, the system oscillator will be stopped while the f sub clock will be on.
rev. 1.00 56 ?a??? ?0? ?01? rev. 1.00 57 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watchdog timer and tms. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the f sub clock will also be on. control register a register pair, smod and smod1, is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 the system clock selection when hlclk is "0" 000: f sub (f l xt or f lirc ) 001: f sub (f l xt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or the lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fast wake-up control (only for hxt) 0: disable 1: enable this is the fast wake-up control bit which determines if the f sub clock source is initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temporary system clock to provide a faster wake up time as the f sub clock is available. bit 3 low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used or 1~2 clock cycles is the lirc oscillator is used.
rev. 1.00 58 ?a??? ?0? ?01? rev. 1.00 59 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom bit 2 hto: high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used or 15~16 clock cycles if the erc or hirc oscillator is used. bit 1 idlen: idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk: system clock selection 0: f h /2~f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f sub clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f sub clock will be selected. when system clock switches from the f h clock to the f sub clock and the f h clock will be automatically switched off to conserve power.
rev. 1.00 58 ?a??? ?0? ?01? rev. 1.00 59 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom smod1 register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 x: unknown bit 7 fsyson: f control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low voltage reset situation occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvr control register software reset fag 0: not occurred 1: occurred this bit is set to 1 if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software-reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program.
rev. 1.00 60 ?a??? ?0? ?01? rev. 1.00 61 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilize and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the lxt or lirc oscillator, to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub, the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fastwake-up function has no effect because the f sub clock is stopped. the fastwake-up enable/disable function is controlled using the fsten bit in the smod1 register. if the hxt oscillator is selected as the normal mode system clock and if the fast wake-up function is enabled, then it will take one to two t sub clock cycles of the lxt or lirc oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the hto fag will switch high and the system will switch over to operating from the hxt oscillator. if the erc/hirc or lirc oscillator is used as the system oscillator, then it will take15~16 clock cycles of the erc/hirc oscillator or 1~2 clock cycles of the lirc osrillator respectively to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no effect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 10? 4 hxt ?y?les 10? 4 hxt ?y?les 1~? hxt ?y?les 1 10? 4 hxt ?y?les 1~? f sub ?y?les (system ?uns wit? f sub frst for 1024 hxt cycles and t?en swit??es ove? to ?un wit? t? e hxt ?lo?k ) 1~? hxt ?y?les erc x 15~16 erc ?y?les 15~16 erc ?y?les 1~? erc ?y?les hirc x 15~16 hirc ?y?les 15~16 hirc ?y?les 1~? hirc ?y?les lirc x 1~? lirc ?y?les 1~? lirc ?y?les 1~? lirc ?y?les lxt x 10? 4 lxt ?y?les 10? 4 lxt ?y?les 1~? lxt ?y?les wake-up times note that if the watchdog timer is disabled, which means that the f sub clock derived from the lxt or lirc oscillator is off, then there will be no fast wake-up function available when the device wakes up from the sleep0 mode.
rev. 1.00 60 ?a??? ?0? ?01? rev. 1.00 61 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom operating mode switching the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the smod1 register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms. the accompanying fowchart shows what happens when the device moves between the various operating modes.

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rev. 1.00 6? ?a??? ?0? ?01? rev. 1.00 6? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or the lirc oscillators and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register .
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rev. 1.00 6? ?a??? ?0? ?01? rev. 1.00 6? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 011, 100, 101, 110 or 111. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
? ? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ? ?? ?? ? - ? ?? ? ? ? ? ?? ?? ? - ?? ?
rev. 1.00 64 ?a??? ?0? ?01? rev. 1.00 65 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 and the wdt and lvd both off. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and the f sub clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped as the wdt is disabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt is enabled and its clock source is derived from the f sub clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in smod1 register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt clock source is derived from the f sub clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared.
rev. 1.00 64 ?a??? ?0? ?01? rev. 1.00 65 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in smod1 register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt clock source is derived from the f sub clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of these devices to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on these devices. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonded pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps.
rev. 1.00 66 ?a??? ?0? ?01? rev. 1.00 67 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, these devices will experience a full system reset, however, if these devices are woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf fags. the pdf fag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up these devices will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the hxt and lxt oscillators both use the same sst counter. for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an off state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. ? if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute first instruction after hto is "1". at this time, the lxt oscillator may not be stabl e if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is 1, the system clock can be switched to the lxt or lirc oscillator after wake up. ? there are peripheral functions, such as wdt and tms, for which the f sys is used. if the system clock source is switched from f h to f sub , the clock source to the peripheral functions mentioned above will change accordingly. ? the on/off condition of f sub depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub .
rev. 1.00 66 ?a??? ?0? ?01? rev. 1.00 67 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the f sub clock. the f sub clock can be sourced from either the lxt or lirc oscillator selected by a confguration option. the lirc internal oscillator has an approximate frequency of 32khz and this specifed internal clock period can vary with v dd , temperature and process variations. the lxt oscillator is supplied by an external 32.768khz crystal. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. this register controls the overall operation of the watchdog timer. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we? we? we1 we0 ws? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 wdt function enable control 10101: disabled 01010: enabled other values: reset mcu if these bits are changed due to adverse environmental conditions, the microcontroller will be reset. the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the smod1 register will be set to 1. bit 2~0 select wdt timeout period 000: 2 8 / f sub 001: 2 10 / f sub 010: 2 12 / f sub 011: 2 14 / f sub 100: 2 15 / f sub 101: 2 16 / f sub 110: 2 17 / f sub 111: 2 18 / f sub these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period.
rev. 1.00 68 ?a??? ?0? ?01? rev. 1.00 69 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom smod1 register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 x: unknown bit 7 fsyson: f control in idle mode described elsewhere bit 6~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag described elsewhere bit 1 lrf: lvr control register software reset fag described elsewhere bit 0 wrf: wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. with regard to the watchdog timer enable/disable function, there are fve bits, we4~we0, in the wdtc register to offer the enable/disable control and reset control of the watchdog timer. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b while the wdt function will be enabled if the we4~we0 bits are equal to 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the device after 2~3 f clock cycles. after power on these bits will have a value of 01010b. wdt function control we4~we0 bits wdt function appli?ation p?og?am enabled 10101b disable 01010b enable any ot?e? value reset ?cu watchdog timer enable/disable control
rev. 1.00 68 ?a??? ?0? ?01? rev. 1.00 69 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 feld, the second is using the watchdog timer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the watchdog timer. that is to use the single clr wdt instruction to clear the wdt contents. the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. clr wdtinst?u?tion 8-stage divide? wdt p?es?ale? we4~we0 bits wdtc registe? reset ?cu lxt f sub f s /? 8 8-to-1 ?ux clr ws?~ws0 (f s /? 8 ~ f s /? 18 ) wdt time-out (? 8 /f s ~ ? 18 /f s ) lirc ? u x low speed os?illato? configu?ation option wat??dog time?
rev. 1.00 70 ?a??? ?0? ?01? rev. 1.00 71 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the is running. one example of this is where after power has been applied and the is already running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the registers remain unchanged allowing the to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=50ms power-on reset timing chart
rev. 1.00 70 ?a??? ?0? ?01? rev. 1.00 71 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom res pin as the reset pin is shared with pb.0, the reset function must be selected using a configuration option. although the microcontroller has an internal rc reset function, if the v dd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant. extern res circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. note: t rstd is power-on delay, typical time=16.7ms res reset timing chart
rev. 1.00 7? ?a??? ?0? ?01? rev. 1.00 7? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the lvr function is always enabled with a specifc lvr voltage, v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally and the lvrf bit in the smod1 register will also be set to 1. for a valid lvr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the a.c. characteristics. if the low supply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected by the lvs bits in the lvrc register. if the lvs7~lvs0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the lvr will reset the device after 2~3 f sub clock cycles. when this happens, the lrf bit in the smod1 register will be set to 1. after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the device enters the power down mode. note: t rstd is power-on delay, typical time=50ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvr voltage select 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other values: generates mcu reset C register is reset to por value when an actual low voltage condition occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 f sub clock cycles. in this situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned register values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 f sub clock cycles. however in this situation the register contents will be reset to the por value.
rev. 1.00 7? ?a??? ?0? ?01? rev. 1.00 7? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? smod1 register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 x: unknown bit 7 fsyson: f control in idle mode described elsewhere bit 6~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low voltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvr control register software reset fag 0: not occurred 1: occurred this bit is set to 1 if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software-reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag described elsewhere watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out fag to will be set to 1. note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to fag will be set to 1. refer to the a.c. characteristics for sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. wdt time-out reset during sleep or idle timing chart
rev. 1.00 74 ?a??? ?0? ?01? rev. 1.00 75 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 powe?-on ?eset u u res o? lvr ?eset du? ing nor? al o? slow ?ode ope?ation 1 u wdt time-out ?eset du?ing nor? al o? slow ?ode ope?ation 1 1 wdt time-out ?eset du?ing idle o? sleep ?ode ope?ation u stands fo? un??anged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p?og?am counte? reset to ze?o inte??upts all inte??upts will be disabled wdt ? time base clea? afte? ?eset? wdt begins ?ounting time ? ?odules time ? ?odules will be tu? ned off input/output po?ts i/o po?ts will be setup as inputs sta?k pointe? sta?k pointe? will point to t?e top of t?e sta?k the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects the microcontroller internal registers. register reset status table register HT66F60A ht66f70a power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) iar0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ?p0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu iar1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ?p1l 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu ?p1h 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu iar? xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ?p?l 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu ?p?h 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp --xx xxxx --uu uuuu --uu uuuu --uu uuuu tbhp -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu status xx00 xxxx uuuu uuuu uu1u uuuu uu11 uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---u bp ---- --00 ---- --00 ---- --00 ---- --uu
rev. 1.00 74 ?a??? ?0? ?01? rev. 1.00 75 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom register HT66F60A ht66f70a power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu -000 0000 -000 0000 -000 0000 -uuu uuuu pf -111 1111 -111 1111 -111 1111 -uuu uuuu pfc -111 1111 -111 1111 -111 1111 -uuu uuuu pgpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pg 1111 1111 1111 1111 1111 1111 uuuu uuuu pgc 1111 1111 1111 1111 1111 1111 uuuu uuuu phpu --00 0000 --00 0000 --00 0000 --uu uuuu ph --11 1111 --11 1111 --11 1111 --uu uuuu phc --11 1111 --11 1111 --11 1111 --uu uuuu integ 0000 0000 0000 0000 0000 0000 uuuu uuuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc? 0000 0000 0000 0000 0000 0000 uuuu uuuu intc? -000 -000 -000 -000 -000 -000 -uuu -uuu ?fi0 0000 0000 0000 0000 0000 0000 uuuu uuuu ?fi1 -000 -000 -000 -000 -000 -000 -uuu -uuu ?fi? 0000 0000 0000 0000 0000 0000 uuuu uuuu ?fi? -000 -000 -000 -000 -000 -000 -uuu -uuu ?fi4 0000 0000 0000 0000 0000 0000 uuuu uuuu s?od 0000 0011 0000 0011 0000 0011 uuuu uuuu s?od1 0--- -x00 0--- -1uu 0--- -uuu u--- -uuu s?od? ---- ---0 ---- ---0 ---- ---0 ---- ---u lvrc 0101 0101 uuuu uuuu 0101 0101 uuuu uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu eea -000 0000 -000 0000 -000 0000 -uuu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu cp0c -000 ---1 -000 ---1 -000 ---1 -uuu ---u cp1c -000 ---1 -000 ---1 -000 ---1 -uuu ---u
rev. 1.00 76 ?a??? ?0? ?01? rev. 1.00 77 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom register HT66F60A ht66f70a power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) t?1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1c? 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1dh ---- --00 ---- --00 ---- --00 ---- --uu t?1al 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1ah ---- --00 ---- --00 ---- --00 ---- --uu t?1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1bh ---- --00 ---- --00 ---- --00 ---- --uu t??c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- t??c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t??dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t??dh 0000 0000 0000 0000 0000 0000 uuuu uuuu t??al 0000 0000 0000 0000 0000 0000 uuuu uuuu t??ah 0000 0000 0000 0000 0000 0000 uuuu uuuu t??rp 0000 0000 0000 0000 0000 0000 uuuu uuuu t??c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t??c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t??dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t??dh ---- --00 ---- --00 ---- --00 ---- --uu t??al 0000 0000 0000 0000 0000 0000 uuuu uuuu t??ah ---- --00 ---- --00 ---- --00 ---- --uu t?0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t?nc1 0000 0000 0000 0000 0000 0000 uuuu uuuu t?0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t?0dh ---- --00 ---- --00 ---- --00 ---- --uu t?0al 0000 0000 0000 0000 0000 0000 uuuu uuuu t?0ah ---- --00 ---- --00 ---- --00 ---- --uu psc0 ---- --00 ---- --00 ---- --00 ---- --uu tbc0 0--- -000 0--- -000 0--- -000 u--- -uuu tbc1 0--- -000 0--- -000 0--- -000 u--- -uuu psc1 ---- --00 ---- --00 ---- --00 ---- --uu adcr0 0110 0000 0110 0000 0110 0000 uuuu uuuu adcr1 -000 -000 -000 -000 -000 -000 -uuu -uuu adrl (adrfs=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu si?c0 111- 000- 111- 000- 111- 000- uuu- uuu- si?c1 1000 0001 1000 0001 1000 0001 uuuu uuuu si?d xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
rev. 1.00 76 ?a??? ?0? ?01? rev. 1.00 77 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom register HT66F60A ht66f70a power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) si?c?/ si?a 0000 0000 0000 0000 0000 0000 uuuu uuuu i? ctoc 0000 0000 0000 0000 0000 0000 uuuu uuuu spiac0 111- --0- 111- --0- 111- --0- uuu- --u- spiac1 0000 0000 0000 0000 0000 0000 uuuu uuuu spiad 0000 0000 0000 0000 0000 0000 uuuu uuuu farl 0000 0000 0000 0000 0000 0000 uuuu uuuu farh --00 0000 --00 0000 --00 0000 --uu uuuu farh -000 0000 -000 0000 -000 0000 -uuu uuuu fd0l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd0h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd?l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd?h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd?l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd?h 0000 0000 0000 0000 0000 0000 uuuu uuuu tbc? 0--- -000 0--- -000 0--- -000 u--- -uuu sco?c 0000 ---- 0000 ---- 0000 ---- uuuu ---- eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu fc0 0000 0000 0000 0000 0000 0000 uuuu uuuu fc1 0000 0000 0000 0000 0000 0000 uuuu uuuu fc? ---- ---0 ---- ---0 ---- ---0 ---- ---u ifs0 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs1 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs? 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs? 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs4 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs5 0000 0000 0000 0000 0000 0000 uuuu uuuu t?4c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- t?4c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t?4dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t?4dh ---- --00 ---- --00 ---- --00 ---- --uu t?4al 0000 0000 0000 0000 0000 0000 uuuu uuuu t?4ah ---- --00 ---- --00 ---- --00 ---- --uu t?4rp 0000 0000 0000 0000 0000 0000 uuuu uuuu t?5c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- t?5c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t?5dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t?5dh ---- --00 ---- --00 ---- --00 ---- --uu t?5al 0000 0000 0000 0000 0000 0000 uuuu uuuu t?5ah ---- --00 ---- --00 ---- --00 ---- --uu t?5rp 0000 0000 0000 0000 0000 0000 uuuu uuuu pas0 0000 0000 0000 0000 0000 0000 uuuu uuuu pas1 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.00 78 ?a??? ?0? ?01? rev. 1.00 79 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom register HT66F60A ht66f70a power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) pas ? 0000 0000 0000 0000 0000 0000 uuuu uuuu pas ? 0000 0000 0000 0000 0000 0000 uuuu uuuu pbs? 0000 0000 0000 0000 0000 0000 uuuu uuuu pbs? 0000 0000 0000 0000 0000 0000 uuuu uuuu pcs0 0000 0000 0000 0000 0000 0000 uuuu uuuu pcs1 0000 0000 0000 0000 0000 0000 uuuu uuuu pcs? 0000 0000 0000 0000 0000 0000 uuuu uuuu pcs? 0000 0000 0000 0000 0000 0000 uuuu uuuu pds0 0000 0000 0000 0000 0000 0000 uuuu uuuu pds1 0000 0000 0000 0000 0000 0000 uuuu uuuu pds? 0000 0000 0000 0000 0000 0000 uuuu uuuu pds? 0000 0000 0000 0000 0000 0000 uuuu uuuu pes0 0000 0000 0000 0000 0000 0000 uuuu uuuu pes1 0000 0000 0000 0000 0000 0000 uuuu uuuu pes? 0000 0000 0000 0000 0000 0000 uuuu uuuu pes? 0000 0000 0000 0000 0000 0000 uuuu uuuu pfs0 0000 0000 0000 0000 0000 0000 uuuu uuuu pgs0 0000 0000 0000 0000 0000 0000 uuuu uuuu pgs1 0000 0000 0000 0000 0000 0000 uuuu uuuu pgs? 0000 0000 0000 0000 0000 0000 uuuu uuuu pgs? 0000 0000 0000 0000 0000 0000 uuuu uuuu phs0 0000 0000 0000 0000 0000 0000 uuuu uuuu phs1 0000 0000 0000 0000 0000 0000 uuuu uuuu phs? 0000 0000 0000 0000 0000 0000 uuuu uuuu note: - not implement u means unchanged x means unknown input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. these devices provide bidirectional input/output lines labeled with port names pa~ph these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten.
rev. 1.00 78 ?a??? ?0? ?01? rev. 1.00 79 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom i/o port register list register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu6 pawu5 pawu4 pawu ? pawu ? pawu1 pawu0 papu papu7 papu6 papu5 papu4 papu ? papu ? papu1 papu0 pa pa7 pa6 pa5 pa4 pa ? pa ? pa1 pa0 pac pac7 pac6 pac5 pac4 pac ? pac ? pac1 pac0 pbpu pbpu7 pbpu6 pbpu5 pbpu4 pbpu? pbpu? pbpu1 pbpu0 pb pb7 pb6 pb5 pb4 pb? pb? pb1 pb0 pbc pbc7 pbc6 pbc5 pbc4 pbc? pbc? pbc1 pbc0 pcpu pcpu7 pcpu6 pcpu5 pcpu4 pcpu? pcpu? pcpu1 pcpu0 pc pc7 pc6 pc5 pc4 pc? pc? pc1 pc0 pcc pcc7 pcc6 pcc5 pcc4 pcc? pcc? pcc1 pcc0 pdpu pdpu7 pdpu6 pdpu5 pdpu4 pdpu? pdpu? pdpu1 pdpu0 pd pd7 pd6 pd5 pd4 pd? pd? pd1 pd0 pdc pdc7 pdc6 pdc5 pdc4 pdc? pdc? pdc1 pdc0 pepu pepu7 pepu6 pepu5 pepu4 pepu? pepu? pepu1 pepu0 pe pe7 pe6 pe5 pe4 pe? pe? pe1 pe0 pec pec7 pec6 pec5 pec4 pec? pec? pec1 pec0 pfpu pfpu6 pfpu5 pfpu4 pfpu? pfpu? pfpu1 pfpu0 pf pf6 pf5 pf4 pf? pf? pf1 pf0 pfc pfc6 pfc5 pfc4 pfc? pfc? pfc1 pfc0 pgpu pgpu7 pgpu6 pgpu5 pgpu4 pgpu? pgpu? pgpu1 pgpu0 pg pg7 pg6 pg5 pg4 pg? pg? pg1 pg0 pgc pgc7 pgc6 pgc5 pgc4 pgc? pgc? pgc1 pgc0 phpu phpu5 phpu4 phpu? phpu? phpu1 phpu0 ph ph5 ph4 ph? ph? ph1 ph0 phc phc5 phc4 phc? phc? phc1 phc0 : unimplemented, read as 0 pawun: pa wake-up function control 0: disable 1: enable pan/pbn/pcn/pdn/pen/pfn/pgn/phn: i/o data bit 0: data 0 1: data 1 pacn/pbcn/pccn/pdcn/pecn/pfcn/pgcn/phcn: i/o type selection 0: output 1: input papun/pbpun/pcpun/pdpun/pepun/pfpun/pgpun/phpun: pull-high function control 0: disable 1: enable
rev. 1.00 80 ?a??? ?0? ?01? rev. 1.00 81 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu~phpu, and are implemented using weak pmos transistors. port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name pawu7 pawu6 pawu5 pawu4 pawu ? pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu: port a bit 7~bit 0 wake-up control 0: disable 1: enable i/o port control registers each port has its own control register, known as pac~phc, which controls the input/output configuration. with this control register, each i/o pin with or without pull-high resistors can be reconfigured dynamically under software control. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. for these pins, the chosen function of the multi-function i/o pins is selected by a series of regiters via the application program control. pin-shared function selection register the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. the device includes port x output function slsection register n, labeled as pxsn, and input function selection register i, labeled as ifsi, which can
rev. 1.00 80 ?a??? ?0? ?01? rev. 1.00 81 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom select the functions of the pin-shared function pins. when the pin-shared input function is selected to be used, the corresponding input and output functions selection should be properly managed. for example, if the i 2 c sda line is used, the corresponding output pin-shared function should be configured as the sdi/sda function by configuring the pxsn register and the sda signal intput should be properly selected using the ifsi register. however, if the external interrupt function is selected to be used, the relevant output pin-shared function should be selected as an i/o function and the interrupt input signal should be selected. register name bit 7 6 5 4 3 2 1 0 pas0 pa1s ? pa1s ? pa1s1 pa1s0 d? d? d1 d0 pas1 pa ?s? pa ?s? pa ?s1 pa ?s0 d? d? d1 d0 pas ? pa5s ? pa5s ? pa5s1 pa5s0 pa4s ? pa4s ? pa4s1 pa4s0 pas ? pa7s ? pa7s ? pa7s1 pa7s0 pa6s ? pa6s ? pa6s1 pa6s0 pbs? pb5s? pb5s? pb5s1 pb5s0 d? d? d1 d0 pbs? pb7s? pb7s? pb7s1 pb7s0 pb6s? pb6s? pb6s1 pb6s0 pcs0 pc1s? pc1s? pc1s1 pc1s0 pc0s? pc0s? pc0s1 pc0s0 pcs1 pc?s? pc?s? pc?s1 pc?s0 pc?s? pc?s? pc?s1 pc?s0 pcs? pc5s? pc5s? pc5s1 pc5s0 pc4s? pc4s? pc4s1 pc4s0 pcs? pc7s? pc7s? pc7s1 pc7s0 pc6s? pc6s? pc6s1 pc6s0 pds0 pd1s? pd1s? pd1s1 pd1s0 pd0s? pd0s? pd0s1 pd0s0 pds1 pd?s? pd?s? pd?s1 pd?s0 pd?s? pd?s? pd?s1 pd?s0 pds? pd5s? pd5s? pd5s1 pd5s0 pd4s? pd4s? pd4s1 pd4s0 pds? pd7s? pd7s? pd7s1 pd7s0 pd6s? pd6s? pd6s1 pd6s0 pes0 pe1s? pe1s? pe1s1 pe1s0 pe0s? pe0s? pe0s1 pe0s0 pes1 pe?s? pe?s? pe?s1 pe?s0 d? d? d1 d0 pes? pe5s? pe5s? pe5s1 pe5s0 pe4s? pe4s? pe4s1 pe4s0 pes? pe7s? pd7s? pe7s1 pe7s0 pe6s? pe6s? pe6s1 pe6s0 pfs0 pf1s? pf1s? pf1s1 pf1s0 pf0s? pf0s? pf0s1 pf0s0 pgs0 pg1s? pg1s? pg1s1 pg1s0 pg0s? pg0s? pg0s1 pg0s0 pgs1 pg?s? pg?s? pg?s1 pg?s0 d? d? d1 d0 pgs? d7 d6 d5 d4 pg4s? pg4s? pg4s1 pg4s0 pgs? pg7s? pg7s? pg7s1 pg7s0 pg6s? pg6s? pg6s1 pg6s0 phs0 ph1s? ph1s? ph1s1 ph1s0 ph0s? ph0s? ph0s1 ph0s0 phs1 ph?s? ph?s? ph?s1 ph?s0 ph?s? ph?s? ph?s1 ph?s0 phs? ph5s? ph5s? ph5s1 ph5s0 d? d? d1 d0 ifs0 pintbs1 pintbs0 int?s1 int?s0 int1s1 int1s0 int0s1 int0s0 ifs1 tck?s1 tck?s0 tck?s1 tck?s0 tck1s1 tck1s0 tck0s1 tck0s0 ifs? tp?is1 tp?is0 tp1ibs1 tp1ibs0 tp1ias1 tp1ias0 d1 d0 ifs? d7 d6 tp5is1 tp5is0 tp4is1 tp4is0 d1 d0 ifs4 d7 d6 sdis1 sdis0 scks1 scks0 scsbs1 scsbs0 ifs5 d7 d6 sdias1 sdias0 sckas1 sckas0 scsabs1 scsabs0
rev. 1.00 8? ?a??? ?0? ?01? rev. 1.00 8? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? pas0 bit 7 6 5 4 3 2 1 0 name pa1s ? pa1s ? pa1s1 pa1s0 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pa1s3~pa1s0: port a1 function selection 0000: i/o 0001: tp1a 0011: an1 others: reserved bit 3~0 reserved bits, can be read and written ? pas1 bit 7 6 5 4 3 2 1 0 name pa ?s? pa ?s? pa ?s1 pa ?s0 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pa3s3~pa3s0: port a3 function selection 0000: i/o 0011: an3 0111: c0n 1111: an3 and c0n others: reserved bit 3~0 reserved bits, can be read and written ? pas2 bit 7 6 5 4 3 2 1 0 name pa5s ? pa5s ? pa5s1 pa5s0 pa4s ? pa4s ? pa4s1 pa4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pa5s3~pa5s0: port a5 function selection 0000: i/o 0001: sdo 0010: c1x 0011: an5 others: reserved bit 3~0 pa4s3~pa4s0: port a4 function selection 0000: i/o 0011: an4 others: reserved
rev. 1.00 8? ?a??? ?0? ?01? rev. 1.00 8? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? pas3 bit 7 6 5 4 3 2 1 0 name pa7s ? pa7s ? pa7s1 pa7s0 pa6s ? pa6s ? pa6s1 pa6s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pa7s3~pa7s0: port a7 function selection 0000: i/o 0010: sck/scl 0011: an7 others: reserved bit 3~0 pa6s3~pa6s0: port a6 function selection 0000: i/o 0010: sdi/sda 0011: an6 others: reserved ? pbs2 bit 7 6 5 4 3 2 1 0 name pb5s? pb5s? pb5s1 pb5s0 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pb5s3~pb5s0: port b5 function selection 0000: i/o 0001: scs others: reserved bit 3~0 reserved bits, can be read and written ? pbs3 bit 7 6 5 4 3 2 1 0 name pb7s? pb7s? pb7s1 pb7s0 pb6s? pb6s? pb6s1 pb6s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pb7s3~pb7s0: port b7 function selection 0000: i/o 0010: sdi/sda others: reserved bit 3~0 pb6s3~pb6s0: port b6 function selection 0000: i/o 0001: sdo others: reserved
rev. 1.00 84 ?a??? ?0? ?01? rev. 1.00 85 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? pcs0 bit 7 6 5 4 3 2 1 0 name pc1s? pc1s? pc1s1 pc1s0 pc0s? pc0s? pc0s1 pc0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pc1s3~pc1s0: port c1 function selection 0000: i/o 0001: tp1b 0010: tp1bb 0011: scom1 others: reserved bit 3~0 pc0s3~pc0s0: port c0 function selection 0000: i/o 0001: tp1b 0010: tp1bb 0011: scom0 others: reserved ? pcs1 bit 7 6 5 4 3 2 1 0 name pc?s? pc?s? pc?s1 pc?s0 pc?s? pc?s? pc?s1 pc?s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pc3s3~pc3s0: port c3 function selection 0000: i/o 0001: tp2 0010: c1x 0100: tp1b others: reserved bit 3~0 pc2s3~pc2s0: port c2 function selection 0000: i/o 0001: pck 0010: c0x others: reserved ? pcs2 bit 7 6 5 4 3 2 1 0 name pc5s? pc5s? pc5s1 pc5s0 pc4s? pc4s? pc4s1 pc4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pc5s3~pc5s0: port c5 function selection 0000: i/o 0001: pck 0010: tp0 0100: tp1b 0101: tp0b 0110: tp1bb others: reserved bit 3~0 pc4s3~pc4s0: port c4 function selection 0000: i/o 0001: tp2 0010: tp2b others: reserved
rev. 1.00 84 ?a??? ?0? ?01? rev. 1.00 85 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? pcs3 bit 7 6 5 4 3 2 1 0 name pc7s? pc7s? pc7s1 pc7s0 pc6s? pc6s? pc6s1 pc6s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pc7s3~pc7s0: port c7 function selection 0000: i/o 0001: tp1a 0011: scom3 others: reserved bit 3~0 pc6s3~pc6s0: port c6 function selection 0000: i/o 0001: tp0 0010: tp0b 0011: scom2 others: reserved ? pds0 bit 7 6 5 4 3 2 1 0 name pd1s? pd1s? pd1s1 pd1s0 pd0s? pd0s? pd0s1 pd0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pd1s3~pd1s0: port d1 function selection 0000: i/o 0001: tp2 0010: sck/scl 0100: sdo 0101: tp2b others: reserved bit 3~0 pd0s3~pd0s0: port d0 function selection 0000: i/o 0001: tp3 0010: scs 0100: tp3b others: reserved ? pds1 bit 7 6 5 4 3 2 1 0 name pd?s? pd?s? pd?s1 pd?s0 pd?s? pd?s? pd?s1 pd?s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pd3s3~pd3s0: port d3 function selection 0000: i/o 0001: tp3 0010: sck/scl 0100: sdo 0101: tp3b others: reserved bit 3~0 pd2s3~pd2s0: port d2 function selection 0000: i/o 0010: sdi/sda others: reserved
rev. 1.00 86 ?a??? ?0? ?01? rev. 1.00 87 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? pds2 bit 7 6 5 4 3 2 1 0 name pd5s? pd5s? pd5s1 pd5s0 pd4s? pd4s? pd4s1 pd4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pd5s3~pd5s0: port d5 function selection 0000: i/o 0001: tp0 0010: tp0b others: reserved bit 3~0 pd4s3~pd4s0: port d4 function selection 0000: i/o 0001: tp2 0010: tp2b others: reserved ? pds3 bit 7 6 5 4 3 2 1 0 name pd7s? pd7s? pd7s1 pd7s0 pd6s? pd6s? pd6s1 pd6s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pd7s3~pd7s0: port d7 function selection 0000: i/o 0001: scs others: reserved bit 3~0 pd6s3~pd6s0: port d6 function selection 0000: i/o 0010: sck/scl others: reserved ? pes0 bit 7 6 5 4 3 2 1 0 name pe1s? pe1s? pe1s1 pe1s0 pe0s? pe0s? pe0s1 pe0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pe1s3~pe1s0: port e1 function selection 0000: i/o 0001: scka others: reserved bit 3~0 pe0s3~pe0s0: port e0 function selection 0000: i/o 0001: scsa others: reserved
rev. 1.00 86 ?a??? ?0? ?01? rev. 1.00 87 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? pes1 bit 7 6 5 4 3 2 1 0 name pe?s? pe?s? pe?s1 pe?s0 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pe3s3~pe3s0: port e3 function selection 0000: i/o 0001: sdoa others: reserved bit 3~0 reserved bits, can be read and written. ? pes2 bit 7 6 5 4 3 2 1 0 name pe5s? pe5s? pe5s1 pe5s0 pe4s? pe4s? pe4s1 pe4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pe5s3~pe5s0: port e5 function selection 0000: i/o 0001: tp3 0010: tp3b others: reserved bit 3~0 pe4s3~pe4s0: port e4 function selection 0000: i/o 0001: tp1b 0010: tp1bb others: reserved ? pes3 bit 7 6 5 4 3 2 1 0 name pe7s? pe7s? pe7s1 pe7s0 pe6s? pe6s? pe6s1 pe6s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pe7s3~pe7s0: port e7 function selection 0000: i/o 0011: an9 others: reserved bit 3~0 pe6s3~pe6s0: port e6 function selection 0000: i/o 0011: an8 others: reserved
rev. 1.00 88 ?a??? ?0? ?01? rev. 1.00 89 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? pfs0 bit 7 6 5 4 3 2 1 0 name pf1s? pf1s? pf1s1 pf1s0 pf0s? pf0s? pf0s1 pf0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pf1s3~pf1s0: port f1 function selection 0000: i/o 0011: an11 0111: c1p 1111: an11 and c1p others: reserved bit 3~0 pf0s3~pf0s0: port f0 function selection 0000: i/o 0011: an10 0111:c1n 1111: an10 and c1n others: reserved ? pgs0 bit 7 6 5 4 3 2 1 0 name pg1s? pg1s? pg1s1 pg1s0 pg0s? pg0s? pg0s1 pg0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pg1s3~pg1s0: port g1 function selection 0000: i/o 0001: c1x others: reserved bit 3~0 pg0s3~pg0s0: port g0 function selection 0000: i/o 0001:c0x others: reserved ? pgs1 bit 7 6 5 4 3 2 1 0 name pg?s? pg?s? pg?s1 pg?s0 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pg3s3~pg3s0: port g3 function selection 0000: i/o 0001: tp4 0010: tp4b others: reserved bit 3~0 reserved bits, can be read and written.
rev. 1.00 88 ?a??? ?0? ?01? rev. 1.00 89 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? pgs2 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 pg4s? pg4s? pg4s1 pg4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 reserved bits, can be read and written. bit 3~0 pg4s3~pg4s0: port g4 function selection 0000: i/o 0001: tp4 0010: tp4b others: reserved ? pgs3 bit 7 6 5 4 3 2 1 0 name pg7s? pg7s? pg7s1 pg7s0 pg6s? pg6s? pg6s1 pg6s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 pg7s3~pg7s0: port g7 function selection 0000: i/o 0001: tp5 0010: tp5b others: reserved bit 3~0 pg6s3~pg6s0: port g6 function selection 0000: i/o 0001: tp5 0010: tp5b others: reserved ? phs0 bit 7 6 5 4 3 2 1 0 name ph1s? ph1s? ph1s1 ph1s0 ph0s? ph0s? ph0s1 ph0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 ph1s3~ph1s0: port h1 function selection 0000: i/o 0011: an2 0111: c0p 1111: an2 and c0p others: reserved bit 3~0 ph0s3~ph0s0: port h0 function selection 0000: i/o 0001: tp0 0010: c0x 0011: an0/vref 0100: tp0b others: reserved
rev. 1.00 90 ?a??? ?0? ?01? rev. 1.00 91 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? phs1 bit 7 6 5 4 3 2 1 0 name ph?s? ph?s? ph?s1 ph?s0 ph?s? ph?s? ph?s1 ph?s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 ph3s3~ph3s0: port h3 function selection 0000: i/o 0001: scka others: reserved bit 3~0 ph2s3~ph2s0: port h2 function selection 0000: i/o 0001: scsa others: reserved ? phs2 bit 7 6 5 4 3 2 1 0 name ph5s? ph5s? ph5s1 ph5s0 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 ph5s3~ph5s0: port h5 function selection 0000: i/o 0001: sdoa others: reserved bit 3~0 reserved bits, can be read and written. ? ifs0 bit 7 6 5 4 3 2 1 0 name pintbs1 pintbs0 int?s1 int?s0 int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pintbs1~pintbs0: pint input source pin selection 00: pc3 others: pc4 bit 5~4 int2s1~int2s0: int2 input source pin selection 00: pc4 others: pe2 bit 3~2 int1s1~int1s0: int1 input source pin selection 00: pa4 01: pc5 10: pe1 11: pe7 bit 1~0 int0s1~int0s0: int0 input source pin selection 00: pa3 01: pc4 10: pe0 11: pe6
rev. 1.00 90 ?a??? ?0? ?01? rev. 1.00 91 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? ifs1 bit 7 6 5 4 3 2 1 0 name tck?s1 tck?s0 tck?s1 tck?s0 tck1s1 tck1s0 tck0s1 tck0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tck3s1~tck3s0: tck3 input source pin selection 00: pc4 others: pe3 bit 5~4 tck2s1~tck2s0: tck2 input source pin selection 00: pc2 others: pd0 bit 3~2 tck1s1~tck1s0: tck1 input source pin selection 00: pa4 others: pd3 bit 1~0 tck0s1~tck0s0: tck0 input source pin selection 00: ph1 others: pd2 ? ifs2 bit 7 6 5 4 3 2 1 0 name tp?is1 tp?is0 tp1ibs1 tp1ibs0 tp1ias1 tp1ias0 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tp2is1~tp2is0: tp2i input source pin selection 00: pc3 01: pc4 10: pd1 11: pd4 bit 5~4 tp1ibs1~tp1ibs0: tp1ib input source pin selection 00: pc0 01: pc1 10: pc5 11: pe4 bit 3~2 tp1ias1~tp1ias0: tp1ia input source pin selection 00: pa1 others: pc7 bit 1~0 reserved bits, can be read and written. ? ifs3 bit 7 6 5 4 3 2 1 0 name d7 d6 tp5is1 tp5is0 tp4is1 tp4is0 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 reserved bits, can be read and written. bit 5~4 tp5is1~tp5is0: tp5i input source pin selection 00: pg6 others: pg7 bit 3~2 tp4is1~tp4is0: tp4i input source pin selection 00: pg3 others: pg4 bit 1~0 reserved bits, can be read and written.
rev. 1.00 9? ?a??? ?0? ?01? rev. 1.00 9? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? ifs4 bit 7 6 5 4 3 2 1 0 name d7 d6 sdis1 sdis0 scks1 scks0 scsbs1 scsbs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 reserved bits, can be read and written. bit 5~4 sdis1~sdis0: sdi/sda input source pin selection 00: pa6 01: pb7 others: pd2 bit 3~2 scks1~scks0: sck/scl input source pin selection 00: pa7 01: pd3 10: pd1 11: pd6 bit 1~0 scsbs1~scsbs0: scs input source pin selection 00: pb5 01: pd0 others: pd7 ? ifs5 bit 7 6 5 4 3 2 1 0 name d7 d6 sdias1 sdias0 sckas1 sckas0 scsabs1 scsabs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 reserved bits, can be read and written. bit 5~4 sdias1~sdias0: sdia input source pin selection 00: pe2 others: ph4 bit 3~2 sckas1~sckas0: scka input source pin selection 00: pe1 others: ph3 bit 1~0 scsabs1~scsabs0: scsa input source pin selection 00: pe0 others: ph2
rev. 1.00 9? ?a??? ?0? ?01? rev. 1.00 9? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ? ? ? ?? generic input/output structure

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? ? ? ? - ? ? - ? ? ? ? a/d input/output structure
rev. 1.00 94 ?a??? ?0? ?01? rev. 1.00 95 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom programming considerations within the user program, one of the things frst to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set to high. this means that all i/o pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer modules C tm one of the most fundamental functions in any microcontroller devices is the ability to control and measure time. to implement time related functions each device includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either multiple interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact and standard tm sections. introduction the devices contain from two to six tms depending upon which device is selected with each tm having a reference name of tm0~tm5. each individual tm can be categorised as a certain type, namely compact type tm, standard type tm or enhanced type tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compact, standard and enhanced tms will be described in this section, the detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. tm function ctm stm etm time ?/counte? i/p captu ?e compa?e ?at?? output pw? c?annels 1 1 ? single pulse output 1 ? pw? alignment edge edge edge & cent?e pw? adjustment pe?iod & duty duty o? pe?iod duty o? pe?iod duty o? pe?iod tm function summary
rev. 1.00 94 ?a??? ?0? ?01? rev. 1.00 95 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom each device in the series contains a specifc number of either compact type, standard type and enhanced type tm unit which are shown in the table together with their individual reference name, tm0~tm5. device tm0 tm1 tm2 tm3 tm4 tm5 HT66F60A 10-bit ct? 10-bit et? 16-bit st? 10-bit ct? 16-bit st? 16-bit st? ht66f70a tm name/type reference tm operation the different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tmn control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f sub clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact type tm has two internal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin.
rev. 1.00 96 ?a??? ?0? ?01? rev. 1.00 97 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom tm external pins each of the tms, irrespective of what type, has two tm input pins, with the label tckn and tpni respectively. the tm input pin, tckn, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tckn pin is also used as the external trigger input pin in single pulse mode for the stm and etm. the other tm input pin, tpni, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register. the tms each have one or more output pins with the label tpn and tpnb respectively. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. the corresponding selection bits in the pin-shared function registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and device is different, the details are provided in the accompanying table. device ctm etm stm registers HT66F60A ht66f70a tp0? tp0b? tck0 tp?? tp?b? tck? tp1a? tp1ia? tck1 tp1b? tp1bb? tp1ib tp?? tp?b? tp?i? tck? tp4? tp4b? tp4i? tck4 tp5? tp5b? tp5i? tck5 ifsi tm input/output pins
rev. 1.00 96 ?a??? ?0? ?01? rev. 1.00 97 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom tm input/output pin control selecting to have a tm input/output or whether to retain its other shared function is implemented using one or two registers, with the corresponding selection bits in each pin-shared function register corresponding to a tm input/output pin. confguring the selection bits correctly will setup the corresponding pin as a tm input/output. the details of the pin-shared function selection are described in the pin-shared function section. ctm (tmn) tckn tpn tpnb ccr output ccr inve?ted output ctm function pin control block diagram (n=0 or 3) stm (tmn) tckn tpn tpnb tpni ccr ?aptu?e input ccr output ccr inve?ted output stm function pin control block diagram (n=2, 4, 5) etm (tm1) tck1 tp1a tp1ia tp1b tp1bb tp1ib ccra ?aptu?e input ccra output ccrb ?aptu?e input ccrb output ccrb inve?ted output etm function pin control block diagram
rev. 1.00 98 ?a??? ?0? ?01? rev. 1.00 99 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. data bus 8 - bit buffe? t?xdh t?xdl t?xbh t?xbl t?xah t?xal t? counte? registe? ( read only ) t? ccra registe? ( read / w?ite ) t? ccrb registe? ( read / w?ite ) as the ccra and ccrb registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way as described above, it is recommended to use the "mov" instruction to access the ccra and ccrb low byte registers, named tmxal and tmxbl, using the following access procedures. accessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values. the following steps show the read and write procedures: ? writing data to ccrb or ccra ? step 1. write data to low byte tmxal or tmxbl C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte tmxah or tmxbh C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccrb or ccra ? step 1. read data from the high byte tmxdh, tmxah or tmxbh C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxbl C this step reads data from the 8-bit buffer.
rev. 1.00 98 ?a??? ?0? ?01? rev. 1.00 99 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom compact type tm C ctm although the simplest form of the two tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive two external output pins. these two external output pins can be the same signal or the inverse signal. device tm type tm name tm input pin tm output pin HT66F60A ht66f70a 10-bit ct? t?0? t?? tck0? tp0i; tck?? tp?i tp0? tp0b; tp?? tp?b
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? - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? - ? ?? ? ?? compact type tm block diagram (n=0 or 3) compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.00 100 ?a??? ?0? ?01? rev. 1.00 101 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom compact type tm register description overall operation of the compact tm is controlled using six registers. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t?nc0 tnpau tnck? tnck1 tnck0 tnon tnrp? tnrp1 tnrp0 t?nc1 tn?1 tn?0 tnio1 tnio0 tnoc tnpol tndpx tncclr t?ndl d7 d6 d5 d4 d? d? d1 d0 t?ndh d9 d8 t?nal d7 d6 d5 d4 d? d? d1 d0 t?nah d9 d8 compact tm register list (n=0 or 3) tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmndh : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmnah : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8
rev. 1.00 100 ?a??? ?0? ?01? rev. 1.00 101 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck? tnck1 tnck0 tnon tnrp? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau: tmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0: select tm0 counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f 101: reserved 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, while f and f are other internal clocks, the details of which can be found in the oscillator section. bit 3 tnon: tmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high.
rev. 1.00 10? ?a??? ?0? ?01? rev. 1.00 10? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom bit 2~0 tnrp2~tnrp0: tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter's highest three bits. the result of this comparison can be selected to clear the internal counter if the tncclr bit is set to zero. setting the tncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tmnc1 register bit 7 6 5 4 3 2 1 0 name tn?1 tn?0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t n m1~t n m0: select tm n operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0: select tpn, tpnb output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.00 10? ?a??? ?0? ?01? rev. 1.00 10? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom in the compare match output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the tnio1 and tnio0 bits only after the tmn has been switched off. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running. bit 3 tnoc: tpn, tpnb output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of he tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol: tpn, tpnb output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn or tpnb output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 tndpx: tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr: select tmn counter clear condition 0: tmn comparator p match 1: tmn comparator a match this bit is used to select the method which clears the counter. remember that the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode.
rev. 1.00 104 ?a??? ?0? ?01? rev. 1.00 105 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom compact type tm operating modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 104 ?a??? ?0? ?01? rev. 1.00 105 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value 0 x? ff ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin time ccrp = 0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed by ccrp value pause resume stop counte? resta?t tncclr = 0 ; tn? [ 1 : 0 ] = 00 output pin set to initial level low if tnoc = 0 output toggle wit? tnaf flag note tnio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnaf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnpol is ?ig? compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=0 or 3
rev. 1.00 106 ?a??? ?0? ?01? rev. 1.00 107 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value 0x?ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin time ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed by ccra value pause resume stop counte? resta?t tncclr = 1; tn? [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle wit? tnaf flag note tnio [1:0] = 10 a?tive hig? output sele?t he?e tnio [1:0] = 11 toggle output sele?t output not affe?ted by tnaf flag. remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin-s?a?ed fun?tion output inve?ts w?en tnpol is ?ig? tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow output does not ??ange compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 5. n=0 or 3
rev. 1.00 106 ?a??? ?0? ?01? rev. 1.00 107 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ctm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod 1?8 ?56 ?84 51? 640 768 896 10?4 duty ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod ccra duty 1?8 ?56 ?84 51? 640 768 896 10?4 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.00 108 ?a??? ?0? ?01? rev. 1.00 109 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin (tnoc=1) time counte? ?lea?ed by ccrp pause resume counte? stop if tnon bit low counte? reset w?en tnon ?etu?ns ?ig? tndpx = 0; tn? [1:0] = 10 pw? duty cy?le set by ccra pw? ?esumes ope?ation output ?ont?olled by ot?e? pin-s?a?ed fun?tion output inve?ts w?en tnpol = 1 pw? pe?iod set by ccrp t? o/p pin (tnoc=0) pwm mode C tndpx=0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0 or 3
rev. 1.00 108 ?a??? ?0? ?01? rev. 1.00 109 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin (tnoc=1) time counte? ?lea?ed by ccra pause resume counte? stop if tnon bit low counte? reset w?en tnon ?etu?ns ?ig? tndpx = 1; tn? [1:0] = 10 pw? duty cy?le set by ccrp pw? ?esumes ope?ation output ?ont?olled by ot?e? pin-s?a?ed fun?tion output inve?ts w?en tnpol = 1 pw? pe?iod set by ccra t? o/p pin (tnoc=0) pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0 or 3
rev. 1.00 110 ?a??? ?0? ?01? rev. 1.00 111 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom standard type tm C stm the standard type tm contains five operating modes, which are compare match output, timer/event counter, capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive one or two external output pins. device tm type tm name tm input pin tm output pin HT66F60A ht66f70a 16-bit st? t??? t?4? t?5 tck?? tp?i; tck4? tp4i; tck5? tp5i tp?? tp?b; tp4? tp4b; tp5? tp5b
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? ? ? ??? ?? ? ??? ? ? ? ? ? ? ? ? ? ? ? ?? ? ?- ? standard type tm block diagram (n=2, 4 or 5) standard tm operation the size of standard tm is 16-bit wide. at the core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 8-bit wide whose value is compared the with highest 8 bits in the counter while the ccra is the sixteen bits and therefore compares all counter bits. the only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.00 110 ?a??? ?0? ?01? rev. 1.00 111 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three or eight ccrp bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t?nc0 tnpau tnck? tnck1 tnck0 tnon t?nc1 tn?1 tn?0 tnio1 tnio0 tnoc tnpol tndpx tncclr t?ndl d7 d6 d5 d4 d? d? d1 d0 t?ndh d15 d14 d1? d1? d11 d10 d9 d8 t?nal d7 d6 d5 d4 d? d? d1 d0 t?nah d15 d14 d1? d1? d11 d10 d9 d8 t?nrp d7 d6 d5 d4 d? d? d1 d0 16-bit standard tm register list (n=2, 4 or 5) tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck? tnck1 tnck0 tnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 tnpau: tmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2, tnck1, tnck0: select tmn counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f 101: reserved 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, while f and f are other internal clocks, the details of which can be found in the oscillator section.
rev. 1.00 11 ? ?a??? ?0? ?01? rev. 1.00 11 ? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom bit 3 tnon: tmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 unimplemented, read as 0 tmnc1 register bit 7 6 5 4 3 2 1 0 name tn?1 tn?0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0: select tmn operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0: select tpn, tpnb output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tpni 01: input capture at falling edge of tpni 10: input capture at falling/rising edge of tpni 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.00 11 ? ?a??? ?0? ?01? rev. 1.00 11 ? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom in the compare match output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the tnio1 and tnio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running. bit 3 tnoc: tpn, tpnb output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol: tpn, tpnb output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn or tpnb output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 tndpx: tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr: select tmn counter clear condition 0: tmn comparator p match 1: tmn comparator a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.00 114 ?a??? ?0? ?01? rev. 1.00 115 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl: tmn counter low byte register bit 7~bit 0 tmn 16-bit counter bit 7~bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d1? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndh: tmn counter high byte register bit 7~bit 0 tmn 16-bit counter bit 15~bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal: tmn ccra low byte register bit 7~bit 0 tmn 16-bit ccra bit 7~bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnah: tmn ccra high byte register bit 7~bit 0 tmn 16-bit ccra bit 15~bit 8 tmnrp register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnrp: tmn ccrp register bit 7~bit 0 tmn ccrp 8-bit register, compared with the tmn counter bit 15~bit 8. comparator p match period 0: 65536 tmn clocks 1~255: 256(1~255) tmn clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counters highest eight bits. the result of this comparison can be selected to clear the internal counter if the tncclr bit is set to zero. setting the tncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.00 114 ?a??? ?0? ?01? rev. 1.00 115 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom standard type tm operating modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to "0". as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 116 ?a??? ?0? ?01? rev. 1.00 117 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ccra ccrp 0xffff counte? ove?flow ccra int. flag tnaf ccrp int. flag tnpf ccrp > 0 counte? ?lea?ed by ccrp value t? o/p pin tnon bit pause counte? reset output pin set to initial level low if tnoc = 0 output toggle wit? tnaf flag he?e tnio1? tnio0 = 11 toggle output sele?t now tnio1? tnio0 = 10 a?tive hig? output sele?t output not affe?ted by tnaf flag. remains hig? until ?eset by tnon bit tncclr = 0; tn?[1:0] = 00 tnpau bit resume stop time ccrp > 0 ccrp = 0 tnpol bit output pin reset to initial value output inve?ts w?en tnpol is ?ig? output ?ont?olled by ot?e? pin-s?a?ed fun?tion counte? value compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=2, 4 or 5
rev. 1.00 116 ?a??? ?0? ?01? rev. 1.00 117 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ccrp ccra 0xffff ccra = 0 counte? ove?flows ccrp int. flag tnpf ccra int. flag tnaf ccra > 0 counte? ?lea?ed by ccra value t? o/p pin tnon bit pause counte? reset output pin reset to initial value output pin set to initial level low if tnoc = 0 output toggle wit? tnaf flag he?e tnio1? tnio0 = 11 toggle output sele?t now tnio1? tnio0 = 10 a?tive hig? output sele?t tnpau bit resume stop time tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow output does not ??ange ccra = 0 output inve?ts w?en tnpol is ?ig? tnpol bit tncclr = 1; tn?[1:0] = 00 output ?ont?olled by ot?e? pin-s?a?ed fun?tion output not affe?ted by tnaf flag ?emains hig? until ?eset by tnon bit counte? value compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1 5. n=2, 4 or 5
rev. 1.00 118 ?a??? ?0? ?01? rev. 1.00 119 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. 16-bit stm, pwm mode, edge-aligned mode, tndpx=0 ccrp 1~255 0 pe?iod ccrp?56 655?6 duty ccra if f sys =16mhz, tm clock source select f sys /4, ccrp=2 and ccra=128, the stm pwm output frequency=(f sys /4)/(2256)=f sys /2048=7.8125khz, duty=128/(2256)=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 16-bit stm, pwm mode, edge-aligned mode, tndpx=1 ccrp 1~255 0 pe?iod ccra duty ccrp?56 655?6 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the (ccrp256) except when the ccrp value is equal to 0.
rev. 1.00 118 ?a??? ?0? ?01? rev. 1.00 119 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc = 1 ) time counte? ?lea?ed by ccrp pause resume counte? stop if tnon bit low counte? reset w?en tnon ?etu?ns ?ig? tndpx = 0 ; tn? [ 1 : 0 ] = 10 pw? duty cy?le set by ccra pw? ?esumes ope?ation output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnpol = 1 pw? pe?iod set by ccrp t? o / p pin ( tnoc = 0 ) pwm mode C tndpx=0 note: 1. here tndpx=0, counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=2, 4 or 5
rev. 1.00 1?0 ?a??? ?0? ?01? rev. 1.00 1?1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc = 1 ) time counte? ?lea?ed by ccra pause resume counte? stop if tnon bit low counte? reset w?en tnon ?etu?ns ?ig? tndpx = 1 ; tn? [ 1 : 0 ] = 10 pw? duty cy?le set by ccrp pw? ?esumes ope?ation output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnpol = 1 pw? pe?iod set by ccra t? o / p pin ( tnoc = 0 ) pwm mode C tndpx=1 note: 1. here tndpx=1 -- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=2, 4 or 5
rev. 1.00 1?0 ?a??? ?0? ?01? rev. 1.00 1?1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom single pulse mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode.

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rev. 1.00 1?? ?a??? ?0? ?01? rev. 1.00 1?? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc = 1 ) time counte? stopped by ccra pause resume counte? stops by softwa?e counte? reset w?en tnon ?etu?ns ?ig? tn? [ 1 : 0 ] = 10 ; tnio [ 1 : 0 ] = 11 pulse widt? set by ccra output inve?ts w?en tnpol = 1 no ccrp inte??upts gene?ated t? o / p pin ( tnoc = 0 ) tckn pin softwa?e t?igge? clea?ed by ccra mat?? tckn pin t?igge? auto . set by tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high. 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. 6. n=2, 4 or 5
rev. 1.00 1?? ?a??? ?0? ?01? rev. 1.00 1?? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom capture input mode to select this mode bits tnm1 and tnm0 in the tmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpni pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpni pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tpni pin the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpni pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpni pin, however it must be noted that the counter will continue to run. the tncclr and tndpx bits are not used in this mode.
rev. 1.00 1?4 ?a??? ?0? ?01? rev. 1.00 1?5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom cou nter va lue yy ccrp tnon tnpau ccrp in t . flag tnpf ccra in t . flag tnaf ccra va lu e time cou nter clea re d b y ccrp p ause r e su m e c ount e r r e se t tnm [1 :0 ] = 01 tm cap ture p in tpn i xx c ount e r s t o p tnio [1 :0 ] va lu e xx yy xx yy ac t i v e edge ac t i v e edge ac t i v e edge 00 ? risi ng edge 01 ? f a lling edge 10 ? b o t h edges 11 ? disabl e c apt u r e capture input mode note: 1. tnm [1:0]=01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n=2, 4 or 5
rev. 1.00 1?4 ?a??? ?0? ?01? rev. 1.00 1?5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom enhanced type tm C etm the enhanced type tm contains five operating modes, which are compare match output, timer/event counter, capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external input pin and can drive three or four external output pins. device tm type tm name. tm input pin tm output pin HT66F60A ht66f70a 10-bit et? t?1 tck1; tp1ia? tp1ib tp1a; tp1b? tp1bb
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? ? ? - - ? enhanced type tm block diagram (n=1) enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. there are three internal comparators with the names, comparator a, comparator b and comparator p. these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore compared with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the t1on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers.
rev. 1.00 1?6 ?a??? ?0? ?01? rev. 1.00 1?7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t?1c0 t1pau tnck? tnck1 tnck0 tnon t1rp? t1rp1 t1rp0 t?1c1 t1a?1 t1a?0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr t?1c? t1b?1 t1b?0 t1bio1 t1bio0 t1boc t1bpol t1pw?1 t1pw?0 t?1dl d7 d6 d5 d4 d? d? d1 d0 t?1dh d10 d9 d8 t?1al d7 d6 d5 d4 d? d? d1 d0 t?1ah d9 d8 t?1bl d7 d6 d5 d4 d? d? d1 d0 t?1bh d9 d8 10-bit enhanced tm register list tm1c0 register bit 7 6 5 4 3 2 1 0 name t1pau t1ck? t1ck1 t1ck0 t1on t1rp? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau: tm1 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0: select tm1 counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f 101: reserved 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, while f and f are other internal clocks, the details of which can be found in the oscillator section.
rev. 1.00 1?6 ?a??? ?0? ?01? rev. 1.00 1?7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom bit 3 t1on: tm1 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run and clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0: tm1 ccrp 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counters highest three bits. the result of this comparison can be selected to clear the internal counter if the t1cclr bit is set to zero. setting the t1cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.00 1?8 ?a??? ?0? ?01? rev. 1.00 1?9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom tm1c1 register bit 7 6 5 4 3 2 1 0 name t1a?1 t1a?0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1am1~t1am0: select tm1 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1am1 and t1am0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1~t1aio0: select tp1a output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1ia 01: input capture at falling edge of tp1ia 10: input capture at falling/rising edge of tp1ia 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register. note that the output level requested by the t1aio1 and t1aio0 bits must be different from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t1aio1 and t1aio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1aio1 and t1aio0 bits are changed when the tm is running.
rev. 1.00 1?8 ?a??? ?0? ?01? rev. 1.00 1?9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom bit 3 t1aoc: tp1a output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol: tp1a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1cdn: tm1 count up or down fag 0: count up 1: count down bit 0 t1cclr: select tm1 counter clear condition 0: tm1 comparatror p match 1: tm1 comparatror a match this bit is used to select the method which clears the counter. remember that the enhanced tm contains three comparators, comparator a, comparator b and comparator p, but only comparator a or comparator p can be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.00 1?0 ?a??? ?0? ?01? rev. 1.00 1?1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom tm1c2 register bit 7 6 5 4 3 2 1 0 name t1b?1 t1b?0 t1bio1 t1bio0 t1boc t1bpol t1pw?1 t1pw?0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1bm1~t1bm0: select tm1 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1bm1 and t1bm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1bio1~t1bio0: select tp1b, tp1bb output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1ib 01: input capture at falling edge of tp1ib 10: input capture at falling/rising edge of tp1ib 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator b. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator b. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register. note that the output level requested by the t1bio1 and t1bio0 bits must be different from the initial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1bio1 and t1bio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1bio1 and t1bio0 bits are changed when the tm is running.
rev. 1.00 1?0 ?a??? ?0? ?01? rev. 1.00 1?1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom bit 3 t1boc: tp1b, tp1bb output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol: tp1b, tp1bb output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b, tp1bb output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1~0 t1pwm1~t1pwm0: select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down tm1dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl: tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm1dh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1dh: tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 tm1al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al: tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0
rev. 1.00 1?? ?a??? ?0? ?01? rev. 1.00 1?? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom tm1ah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1ah: tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 tm1bl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1bl: tm1 ccrb low byte register bit 7~bit 0 tm1 10-bit ccrb bit 7~bit 0 tm1bh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1bh: tm1 ccrb high byte register bit 1~bit 0 tm1 10-bit ccrb bit 9~bit 8 enhanced type tm operating modes the enhanced type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnam1 and tnam0 bits in the tmnc1, and the tnbm1 and tnbm0 bits in the tmnc2 register. etm operation mode ccra compare match output mode ccra timer/ counter mode ccrb pwm output mode ccrb single pulse output mode ccrb input capture mode ccrb compa?e ?at?? output ?ode ccrb time ?/counte? ?ode ccrb pw? output ?ode ccrb single pulse output ?ode ccrb input captu?e ?ode ?: permitted; : not permitted
rev. 1.00 1?? ?a??? ?0? ?01? rev. 1.00 1?? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom compare output mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1/tmnc2 registers should be all cleared to zero. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both the tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf or tnbf interrupt request fag is generated after a compare match occurs from comparator a or comparator b. the tnpf interrupt request flag, generated from a compare match from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the tnaio1 and tnaio0 bits in the tmnc1 register for etm ccra, and the tnbio1 and tnbio0 bits in the tmnc2 register for etm ccrb. the tm output pin can be selected using the tnaio1, tnaio0 bits (for the tpna pin) and tnbio1, tnbio0 bits (for the tp1b, tp1bb pins) to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a or a compare match occurs from comparator b. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnaoc or tnboc bit for tpna or tp1b, tp1bb output pins. note that if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are zero then no pin change will take place.
rev. 1.00 1?4 ?a??? ?0? ?01? rev. 1.00 1?5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value 0 x? ff ccrp ccra tnon tnpau tnapol ccrp int . flag tnpf ccra int . flag tnaf tpna o /p pin time ccrp = 0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed by ccrp value pause resume stop counte? resta?t tncclr = 0; tna? [1 :0 ] = 00 output pin set to initial level low if tnaoc = 0 output toggle wit? tnaf flag note tnaio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnaio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnaf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnapol is ?ig? etm ccra compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=1
rev. 1.00 1?4 ?a??? ?0? ?01? rev. 1.00 1?5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value 0 x? ff ccrp ccrb tnon tnpau tnbpol ccrp int . flag tnpf ccrb int . flag tnbf tpnb o /p pin time ccrp = 0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed by ccrp value pause resume stop counte? resta?t tncclr = 0; tnb? [1 :0 ] = 00 output pin set to initial level low if tnboc = 0 output toggle wit? tnbf flag note tnbio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnbio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnbf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnbpol is ?ig? etm ccrb compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=1
rev. 1.00 1?6 ?a??? ?0? ?01? rev. 1.00 1?7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value 0 x? ff ccrp ccra tnon tnpau tnapol ccrp int . flag tnpf ccra int . flag tnaf tpna o /p pin time ccra = 0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed by ccra value pause resume stop counte? resta?t tncclr = 1; tna? [1 :0 ] = 00 output pin set to initial level low if tnaoc = 0 output toggle wit? tnaf flag note tnaio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnaio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnaf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnapol is ?ig? tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow output does not ??ange etm ccra compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the tpna output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 5. n=1
rev. 1.00 1?6 ?a??? ?0? ?01? rev. 1.00 1?7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value 0 x? ff ccrb ccra tnon tnpau tnbpol ccrb int . flag tnbf ccra int . flag tnaf tpnb o /p pin time ccra = 0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed by ccra value pause resume stop counte? resta?t tncclr = 1; tnb? [1 :0 ] = 00 output pin set to initial level low if tnboc = 0 output toggle wit? tnbf flag note tnbio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnbio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnbf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnbpol is ?ig? no tnaf flag gene?ated on ccra ove?flow etm ccrb compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the tpnb output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 5. n=1
rev. 1.00 1?8 ?a??? ?0? ?01? rev. 1.00 1?9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm mode, the tncclr bit is used to determine in which way the pwm period is controlled. with the tncclr bit set high, the pwm period can be fnely controlled using the ccra registers. in this case the ccrb registers are used to set the pwm duty value (for tpnb and tpnbb output pins). the ccrp bits are not used and tpna output pin is not used. the pwm output can only be generated on the tpnb and tpnbb output pins. with the tncclr bit cleared to zero, the pwm period is set using one of the eight values of the three ccrp bits, in multiples of 128. now both ccra and ccrb registers can be used to setup different duty cycle values to provide dual pwm outputs on their relative tpna, tpnb and tpnbb pins. the tnpwm1 and tnpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is reset to zero. with all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially, thus reducing the level of simultaneous power switching currents. interrupt fags, one for each of the ccra, ccrb and ccrp, will be generated when a compare match occurs from either the comparator a, comparator b or comparator p. the tnaoc and tnboc bits in the tmnc1 and tmnc2 register are used to select the required polarity of the pwm waveform while the two tnaio1, tnaio0 and tnbio1, tnbio0 bits pairs are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnapol and tnbpol bit are used to reverse the polarity of the pwm output waveform.
rev. 1.00 1?8 ?a??? ?0? ?01? rev. 1.00 1?9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom etm, pwm mode, edge-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod 1?8 ?56 ?84 51? 640 768 896 10?4 a duty ccra b duty ccrb if f sys =12mhz, tm clock source select f sys /4, ccrp=100b, ccra=128 and ccrb=256, the tpna pwm output frequency=(f sys /4)/512=f sys /2048=5.8594khz, duty=128/512=25%. the tpnb or tpnbb pwm output frequency=(f sys /4)/512=f sys /2048=5.8594khz, duty=256/512=50%. if the duty value defned by ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. etm, pwm mode, edge-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 pe?iod 1 ? ? 511 51? 10?1 10?? 10?? b duty ccrb etm, pwm mode, center-aligned mode, tncclr=0 ccra 001b 010b 011b 100b 101b 110b 111b 000b pe?iod ?56 51? 768 10?4 1?80 15?6 179? ?046 a duty (ccra?)-1 b duty (ccrb?)-1 etm, pwm mode, center-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 pe?iod ? 4 6 10?? 10?4 ?04? ?044 ?046 b duty (ccrb?)-1
rev. 1.00 140 ?a??? ?0? ?01? rev. 1.00 141 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value ccrp ccra tnon tnpau tnapol ccra int . flag tnaf ccrb int . flag tnbf tpna pin ( tnaoc = 1 ) time counte? clea?ed by ccrp pause resume stop counte? resta?t tncclr = 0; tna? [1 :0 ] = 10 ? tnb? [1 :0 ] = 10 ; tnpw? [1 :0 ] = 00 output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnapol is ?ig? ccrb ccrp int . flag tnpf tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cy?le set by ccra duty cy?le set by ccrb pw? pe?iod set by ccrp duty cy?le set by ccra duty cy?le set by ccra etm pwm mode C edge aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0])=00 or 01 3. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 4. n=1
rev. 1.00 140 ?a??? ?0? ?01? rev. 1.00 141 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counter va lue ccra t n o n t n pau t n bpo l ccrb i n t. f l ag t n b f time cou nte r cle ared by ccra p ause r e su m e s t o p c ount e r r e st a r t tncclr = 1; tnbm [1 :0 ] = 10 ; tnpwm [1 :0 ] = 00 o u t put pi n r e s e t to i n i t i a l v a l u e o u t put c ont ro lled b y o t her p i n - s hared f unc t i o n o u t put in v e rt s w hen t n bpo l i s h i g h ccrb ccra i n t. f l ag t n a f t p n b p i n ( t n b o c = 1 ) t p n b p i n ( t n b o c = 0 ) d u t y c y c l e s e t b y ccrb pw m pe ri od s e t b y ccra etm pwm mode C edge aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnbio [1:0]=00 or 01 3. the ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin 5. n=1
rev. 1.00 14? ?a??? ?0? ?01? rev. 1.00 14? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value ccrp ccra tnon tnpau tnapol ccra int . flag tnaf ccrb int . flag tnbf tpna pin ( tnaoc = 1 ) time pause resume stop counte? resta?t tncclr = 0; tna? [1 :0 ] = 10 ? tnb? [1 :0 ] = 10 ; tnpw? [1 :0 ] = 11 output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnapol is ?ig? ccrb ccrp int . flag tnpf tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cy?le set by ccra duty cy?le set by ccrb pw? pe?iod set by ccrp etm pwm mode C centre aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. tnpwm [1:0]=11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0])=00 or 01 4. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value 6. n=1
rev. 1.00 14? ?a??? ?0? ?01? rev. 1.00 14? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value ccra tnon tnpau tnbpol ccra int . flag tnaf ccrb int . flag tnbf time pause resume stop counte? resta?t tncclr = 1 ; tnb? [ 1 : 0 ] = 10; tnpw? [ 1 : 0 ] = 11 output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion ccrb tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cy?le set by ccrb pw? pe?iod set by ccra output inve?ts w?en tnbpol is ?ig? ccrp int . flag tnpf etm pwm mode C centre aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. tnpwm [1:0]=11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnbio [1:0]=00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value 6. n=1
rev. 1.00 144 ?a??? ?0? ?01? rev. 1.00 145 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom single pulse mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the corresponding tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tpna output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. the trigger for the pulse tpnb output leading edge is a compare match from comparator b, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output of tpna. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge of tpna will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tpna and tpnb or tpnbb will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge of tpna and tpnb or tpnbb. in this way the ccra value can be used to control the pulse width of tpna. the (ccra-ccrb) value can be used to control the pulse width of tpnb and tpnbb. a compare match from comparator a and comparator b will also generate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used. tnon bit 0 1 s/w command settnon o? tckn pin t?ansition ccrb leading edge tnon bit 1 0 ccra t?ailing edge s/w command clrtnon o? ccra compa?e ?at?? tpna output pin tpnb output pin pulse widt? = (ccra-ccrb) value pulse widt? = ccra value counte? value ccrb ccra 0 time tnon = 1 ccrb compa?e ?at?? tnon bit 1 0 s/w command clrtnon o? ccra compa?e ?at?? ccrb t?ailing edge ccra leading edge tpnbb output pin single pulse generation
rev. 1.00 144 ?a??? ?0? ?01? rev. 1.00 145 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counte? value ccrb ccra tnon tnpau tnapol ccrb int . flag tnbf ccra int . flag tnaf tpna pin ( tnaoc = 1 ) time counte? stopped by ccra pause resume counte? stops by softwa?e counte? reset w?en tnon ?etu?ns ?ig? tna? [1 :0 ] = 10 ? tnb? [1 :0 ] = 10 ; tnaio [1 : 0 ] = 11 ? tnbio [1 :0 ] = 11 pulse widt? set by ( ccra -ccrb ) output inve?ts w?en tnbpol = 1 tckn pin softwa?e t?igge? clea?ed by ccra mat?? tckn pin t?igge? auto . set by tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? tnbpol tpna pin ( tnaoc = 0 ) tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) pulse widt? set by ccra output inve?ts w?en tnapol = 1 etm C single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to 11 and can not be changed 6. n=1
rev. 1.00 146 ?a??? ?0? ?01? rev. 1.00 147 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom capture input mode to select this mode bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpnia and tpnib pins, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnaio1, tnaio0 and tnbio1, tnbio0 bits in the tmnc1 and tmnc2 registers. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpnia and tpnib pins, the present value in the counter will be latched into the ccra and ccrb registers and a tm interrupt generated. irrespective of what events occur on the tpnia and tpnib pins the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnaio1, tnaio0 and tnbio1, tnbio0 bits can select the active trigger edge on the tpnia and tpnib pins to be a rising edge, falling edge or both edge types. if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpnia and tpnib pins, however it must be noted that the counter will continue to run. as the tpnia and tpnib pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnaoc, tnboc, tnapol and tnbpol bits are not used in this mode.
rev. 1.00 146 ?a??? ?0? ?01? rev. 1.00 147 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom counter va lue yy ccrp tnon tnpau ccrp in t . flag tnpf ccra in t . flag tnaf ccra va lu e time counter clea re d by ccrp p ause r e su m e c ount e r r e se t tnam [ 1:0] = 01 tm cap ture pin tpnia xx c ount e r s t o p tnaio [1 :0 ] va lu e xx yy xx yy ac t i v e edge ac t i v e edge ac t i v e edge 00 ? risi ng edge 01 ? f a lling edge 10 ? b o t h edges 11 ? disabl e c apt u r e etm ccra capture input mode note: 1. tnam [1:0]=01 and active edge set by the tnaio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function -- tnaoc and tnapol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero 6. n=1
rev. 1.00 148 ?a??? ?0? ?01? rev. 1.00 149 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ccr p c o unt e r o v e r f l o w ccr p i n t . f l ag t n p f ccr b i n t . f l ag t n b f t n o n b i t p a u se c o u n t e r r e se t t n pau b i t r e su m e s t o p y y x x ccr b v a l u e x x t m c apt u r e p i n tpnib y y t n b i o 1 , t n b i o 0 v a l u e 00 - r i s i ng edge 01 - f a l ling edge 11 - d i s abl e c apt u r e a c t i v e edge a c t i v e edge x x 10 - b o t h edges a c t i v e edges y y t n b m 1 , t n b m 0 = 0 1 t i m e c ount e r v a l u e etm ccrb capture input mode note: 1. tnbm [1:0]=01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. tncclr bit not used 4. no output function -- tnboc and tnbpol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero 6. n=1
rev. 1.00 148 ?a??? ?0? ?01? rev. 1.00 149 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom aanlog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the devices contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. part no. input channels a/d channel select bits input pins HT66F60A ht66f70a 1? acs4~acs0 an0~an11 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers. a/d converter register description overall operation of the a/d converter is controlled using four registers. a read only register pair exists to store the adc data 12-bit value. the remaining two registers are control registers which setup the operating and control function of the a/d converter. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adrl (adrfs=0) d? d? d1 d0 adrl (adrfs=1) d7 d6 d5 d4 d? d? d1 d0 adrh (adrfs=0) d11 d10 d9 d8 d7 d6 d5 d4 adrh (adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff acs4 acs? acs? acs1 acs0 adcr1 vbgen adrfs vrefs adck? adck1 adck0 a/d converter register list

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rev. 1.00 150 ?a??? ?0? ?01? rev. 1.00 151 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter, it requires two data registers to store the converted value. these are a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d? d? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d? d? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, pas0~pas3, pes3, pfs0, phs0 to control the function and operation of the a/d converter, two control registers known as adcr0 and adcr1 are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs4~acs0 bits in the adcr0 register defne the adc input channel number. as the device contains only one actual analog to digital converter hardware circuit, each of the individual 12 analog inputs must be routed to the converter. it is the function of the acs4~acs0 bits to determine which analog channel input pins or internal 1.25v is actually connected to the internal a/d converter. the pin-shared function conntrol registers, named pas0~pas3, pes3, pfs0 and phs0, contain the corresponding pin-shared function selection bits which determine which pins on port a, port e, port f and port h are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. confguring the corresponding bit will select the a/d input function or either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.00 150 ?a??? ?0? ?01? rev. 1.00 151 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? adcr0 register bit 7 6 5 4 3 2 1 0 name start eocb adoff acs4 acs? acs? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 0 bit 7 start: start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb: end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running, the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the device power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4~0 acs4~acs0: select a/d channel 00000: an0 00001: an1 00010: an2 00011: an3 00100: an4 00101: an5 00110: an6 00111: an7 01000: an8 01001: an9 01010: an10 01011: an11 011xx: undefned 1xxxx: internal bandgap voltage these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the twelve a/d inputs must be routed to the internal converter using these bits. if the acs4 bit is set high, then the internal bandgap 1.25v will be routed to the a/d converter.
rev. 1.00 15? ?a??? ?0? ?01? rev. 1.00 15? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? adcr1 register bit 7 6 5 4 3 2 1 0 name vbgen adrfs vrefs adck? adck1 adck0 r/w r r/w r/w r/w r/w r/w por 1 1 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 vbgen: internal bandgap voltage control 0: disable 1: enable this bit controls the internal bandgap circuit on/off function to the a/d converter. when the bit is set high the bandgap voltage 1.25v can be used by the a/d converter. if 1.25v is not used by the a/d converter and the lvr/lvd function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. when 1.25v is switched on for use by the a/d converter, a time tbg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 adrfs: adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 4 vrefs: select adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter. if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. bit 3 unimplemented, read as "0" bit 2~0 adck2, adck1, adck0: select adc clock source 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: undefned these three bits are used to select the clock source for the a/d converter.
rev. 1.00 15? ?a??? ?0? ?01? rev. 1.00 15? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom a/d operation the start bit in the adcr0 register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the start bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit in the adcr0 register is used to indicate when the analog to digital conversion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/d clock source is determined by the system clocky, f sys , and by bits adck2~adck0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t adck , is 0.5s, care must be taken for system clock frequencies equal to or greater than 4mhz. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000. doing so will give a/d clock periods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1?hz 1s 2s 4s 8s 16s 32s 64s undefned ??hz 500ns 1s 2s 4s 8s 16s 32s undefned 4?hz ?50ns* 500ns 1s 2s 4s 8s 16s undefned 8?hz 1?5ns* ?50ns* 500ns 1s 2s 4s 8s undefned 1??hz 8?ns* 167ns* ???ns* 667ns 1.33s 2.67s 5.33s undefned a/d clock period examples controlling the power on/off function of the a/d converter circuitry is implemented using the adoff bit in the adcr0 register. this bit must be zero to power on the a/d converter. when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref. the desired selection is made using the vrefs and ph0s3~ph0s0 bits. as the vref pin is pin-shared with other functions, when the vrefs bit is set high and the ph0s3~ph0s0 bits are set to 0011, the vref pin function will be selected and the other pin functions will be disabled automatically.
rev. 1.00 154 ?a??? ?0? ?01? rev. 1.00 155 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port a, port e, port f and port h as well as other functions. the corresponding selection bits in the pas0~pas3, pes3, pfs0 and phs0 registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the corresponding pin is setup to be an a/d converter input, the original pin functions disabled. in this way, pins can be changed under program control to change their function between a/d inputs and other functions. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pac, pec, pfc or phc port control register to enable the a/d input as when the relevant a/d input function selection bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref .
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a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4~acs0 bits which are also contained in the adcr1 and adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the corresponding pin-shared function selection registers. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this.
rev. 1.00 154 ?a??? ?0? ?01? rev. 1.00 155 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data register adrl and adrh can be read to obtain the conversion value. as an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t adck where t adck is equal to the a/d clock period.

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rev. 1.00 156 ?a??? ?0? ?01? rev. 1.00 157 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom programming considerations during microcontroller operations where the a/d converter is not being used, the a/d internal circuitry can be switched off to reduce power consumption, by setting bit adoff high in the adcr0 register. when this happens, the internal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the devices contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb=(v dd or v ref )4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value (v dd or v ref )4096 the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.

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? ideal a/d transfer function
rev. 1.00 156 ?a??? ?0? ?01? rev. 1.00 157 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,03h ; setup phs0 to confgure pin an0 mov phs0,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : jmp start_conversion ; start next a/d conversion
rev. 1.00 158 ?a??? ?0? ?01? rev. 1.00 159 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,03h ; setup phs0 to confgure pin an0 mov phs0,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti
rev. 1.00 158 ?a??? ?0? ?01? rev. 1.00 159 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom comparators two independent analog comparators are contained within these devices. these functions offer fexibility via their register controlled features such as power-down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused.

comparator comparator operation the devices contain two comparator functions which are used to compare two analog voltages and provide an output based on their difference. full control over the two internal comparators is provided via two control registers, cp0c and cp1c, one assigned to each comparator. the comparator output is recorded via a bit in their respective control register, but can also be transferred out onto a shared i/o pin. additional comparator functions include, output polarity, hysteresis functions and power down control. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. as the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level, however, unavoidable input offsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value.
rev. 1.00 160 ?a??? ?0? ?01? rev. 1.00 161 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom comparator registers there are two registers for overall comparator operation, one for each comparator. as corresponding bits in the two registers have identical functions, they following register table applies to both registers. register name bit 7 6 5 4 3 2 1 0 cp0c c0en c0pol c0out c0hyen cp1c c1en c1pol c1out c1hyen comparator registers list cp0c register bit 7 6 5 4 3 2 1 0 name c0en c0pol c0out c0hyen r/w r/w r/w r r/w por 0 0 0 1 bit 7 unimplemented, read as "0" bit 6 c0en: comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the devices enter the sleep or idle mode. bit 5 c0pol: comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c0out bit will refect the non-inverted output condition of the comparator. if the bit is high the comparator c0out bit will be inverted. bit 4 c0out: comparator output bit c0pol=0 0: c0+ < c0- 1: c0+ > c0- c0pol=1 0: c0+ > c0- 1: c0+ < c0- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c0pol bit. bit 3~1 unimplemented, read as "0" bit 0 c0hyen: hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold.
rev. 1.00 160 ?a??? ?0? ?01? rev. 1.00 161 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom cp1c register bit 7 6 5 4 3 2 1 0 name c1en c1pol c1out c1hyen r/w r/w r/w r r/w por 0 0 0 1 bit 7 unimplemented, read as "0" bit 6 c1en: comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the devices enter the sleep or idle mode. bit 5 c1pol: comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c1out bit will refect the non-inverted output condition of the comparator. if the bit is high the comparator c1out bit will be inverted. bit 4 c1out: comparator output bit c1pol=0 0: c1+ < c1- 1: c1+ > c1- c1pol=1 0: c1+ > c1- 1: c1+ < c1- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c1pol bit. bit 3~1 unimplemented, read as "0" bit 0 c1hyen: hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold.
rev. 1.00 16? ?a??? ?0? ?01? rev. 1.00 16? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom comparator interrupt each also possesses its own interrupt function. when any one of the changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state of the c0out or c1out bit and not the output pin which generates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generated interrupt fag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt fag should be frst set high before entering the sleep or idle mode. programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled. serial interface module C sim these devices contain a serial interface module, which includes both the four-line spi interface or two-line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins and therefore the sim interface functional pins must first be selected using the corresponding pin-shared function selection bits. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o pins are selected using pull-high control registers when the sim function is enabled and the corresponding pins are used as sim input pins. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the devices can be either master or slave. although the spi interface specifcation can control multiple slave devices from a single master, but these devices provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices.
rev. 1.00 16? ?a??? ?0? ?01? rev. 1.00 16? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface pins must frst be selected by confguring the pin-shared function selection bits and setting the correct bits in the simc0 and simc2 registers. after the desired spi confguration has been set it can be disabled or enabled using the simen bit in the simc0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to 1 to enable scs pin function, set csen bit to 0 the scs pin will be foating state. the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. spi master/slave connection

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rev. 1.00 164 ?a??? ?0? ?01? rev. 1.00 165 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 si?c0 si?? si?1 si?0 si?deb1 si?deb0 si?en si?d d7 d6 d5 d4 d? d? d1 d0 si?c? d7 d6 ckpolb ckeg ?ls csen wcol trf sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the devices write data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the devices can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmission clock frequency. although not connected with the spi function, the simc0 register is also used to control the peripheral clock prescaler. register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc.
rev. 1.00 164 ?a??? ?0? ?01? rev. 1.00 165 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom simc0 register bit 7 6 5 4 3 2 1 0 name si?? si?1 si?0 si?deb1 si?deb0 si?en r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 bit 7~5 sim2, sim1, sim0: sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f /16 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from tm0. if the spi slave mode is selected then the clock will be supplied by an external master devices. bit 4 unimplemented, read as "0" bit 3~2 simdeb1~simdeb0: i 2 c debounce time selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 simen: sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective.if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0"
rev. 1.00 166 ?a??? ?0? ?01? rev. 1.00 167 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom simc2 register bit 7 6 5 4 3 2 1 0 name d7 d6 ckpolb ckeg ?ls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bit this bit can be read or written by the application program. bit 5 ckpolb: determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg: determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls: spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen: spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and placed into i/o pin or the other functions. if the bit is high the scs pin will be enabled and used as a select pin. bit 1 wcol: spi write collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. bit 0 trf: spi transmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the transmit/receive complete fag and is set 1 automatically when an spi data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt.
rev. 1.00 166 ?a??? ?0? ?01? rev. 1.00 167 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output an scs signal to enable the slave devices before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode.
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rev. 1.00 168 ?a??? ?0? ?01? rev. 1.00 169 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom

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rev. 1.00 168 ?a??? ?0? ?01? rev. 1.00 169 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operate in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. the simdeb1 and simdeb0 bits determine the debounce time of the i 2 c interface. this uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 2 or 4 system clocks. to achieve the required i 2 c data transfer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) no deboun?e f sys > ??hz f sys > 5?hz ? system ?lo?k deboun?e f sys > 4?hz f sys > 10?hz 4 system ?lo?k deboun?e f sys > 8?hz f sys > ?0?hz i 2 c minimum f sys frequency
rev. 1.00 170 ?a??? ?0? ?01? rev. 1.00 171 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom
i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sima, and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 si?c0 si?? si?1 si?0 si?deb1 si?deb0 si?en si?c1 hcf hans hbb htx txak srw ia?wu rxak si?d d7 d6 d5 d4 d? d? d1 d0 si?a iica6 iica5 iica4 iica? iica? iica1 iica0 d0 i 2 c registers list
rev. 1.00 170 ?a??? ?0? ?01? rev. 1.00 171 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom simc0 register bit 7 6 5 4 3 2 1 0 name si?? si?1 si?0 si?deb1 si?deb0 si?en r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 bit 7~5 sim2, sim1, sim0: sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f /16 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as "0" bit 3~2 simdeb1~simdeb0: i 2 c debounce time selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 simen: sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0"
rev. 1.00 17? ?a??? ?0? ?01? rev. 1.00 17? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom simc1 register bit 7 6 5 4 3 2 1 0 name hcf haas hbb htx txak srw ia?wu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf: i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas: i 2 c bus address match fag 0: not address match 1: address match the haas fag is the address match fag. this fag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb: i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a start signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx: select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak: i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 srw: i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is the i 2 c slave read/write flag. this flag determines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the srw fag to determine whether it should be in transmit mode or receive mode. if the srw fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu: i 2 c address match wake-up control 0: disable 1: enable - must be cleared by the application program after wake-up this bit should be set to 1 to enable the i 2 c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation.
rev. 1.00 17? ?a??? ?0? ?01? rev. 1.00 17? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom bit 0 rxak: i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave does not receive acknowledge fag the rxak flag is the receiver acknowledge flag. when the rxak flag is 0, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the devices write data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the devices can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown sima register bit 7 6 5 4 3 2 1 0 name iica6 iica5 iica4 iica? iica? iica1 iica0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x: unknown bit 7~1 iica6~iica0: i 2 c slave address iica6~iica0 is the i 2 c slave address bit 6~bit 0 the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register define the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit this bit can be read or written by user software program.
rev. 1.00 174 ?a??? ?0? ?01? rev. 1.00 175 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom

? ? ? ? ? ?- ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? i 2 c block diagram i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmission, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 and simen bits in the simc0 register to 1 to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt.
rev. 1.00 174 ?a??? ?0? ?01? rev. 1.00 175 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom

? ? ? ? ? ? - ? ? ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defnes the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
rev. 1.00 176 ?a??? ?0? ?01? rev. 1.00 177 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom i 2 c bus read/write signal the srw bit in the simc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the srw fag to determine if it is to be a transmitter or a receiver. if the srw fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1. if the srw fag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0. i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0, before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
rev. 1.00 176 ?a??? ?0? ?01? rev. 1.00 177 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom
? ? ? ? ? ? ? ? - ?
- ? ? note: *when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c communication timing diagram
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i 2 c bus isr fow chart
rev. 1.00 178 ?a??? ?0? ?01? rev. 1.00 179 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom i 2 c time-out control in order to reduce the i 2 c lockup problem due to reception of erroneous clock sources, a time-out function is provided. if the clock source connected to the i 2 c bus is not received for a while, then the i 2 c circuitry and registers will be reset after a certain time-out period. the time-out counter starts to count on an i 2 c bus start & address matchcondition, and is cleared by an scl falling edge. before the next scl falling edge arrives, if the time elapsed is greater than the time-out period specifed by the i2ctoc register, then a time-out condition will occur. the time-out function will stop when an i 2 c stop condition occurs.

i 2 c time-out when an i 2 c time-out counter overfow occurs, the counter will stop and the i2ctoen bit will be cleared to zero and the i2ctf bit will be set high to indicate that a time-out condition has occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrrupt vector. when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out si?d? si?a? si?c0 no ??ange si?c1 reset to por ?ondition i 2 c registers after time-out the i2ctof fag can be cleared by the application program. there are 64 time-out period selections which can be selected using the i2ctos bits in the i2ctoc register. the time-out duration is calculated by the formula: ((1~64) (32/f sub )). this gives a time-out period which ranges from about 1ms to 64ms.
rev. 1.00 178 ?a??? ?0? ?01? rev. 1.00 179 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom i2ctoc register bit 7 6 5 4 3 2 1 0 name i? ctoen i? ctof i? ctos5 i? ctos4 i? ctos? i? ctos? i? ctos1 i? ctos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 i2ctoen: i 2 c time-out control 0: disable 1: enable bit 6 i2ctof: i 2 c time-out fag 0: no time-out occurred 1: time-out occurred bit 5~0 i2ctos5~i2ctos0: i 2 c time-out time selection 2 c time-out clock source is f /32 2 c time-out time is given by: (i2ctos [5:0] +1) (32/f ) peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen using the relevant pin-shared function selection bit. the peripheral clock function is controlled using the tb2en bit in the tbc2 register. the clock source for the peripheral clock output can originate from the system clock f , the instruction clock, the high speed oscillator clock f or the clock which can be selected by the clks11 and clks10 bits in the psc1 register. the tb2en bit in the tbc2 register is the overall on/off control, setting tb2en bit to 1 enables the peripheral clock while setting tb2en bit to 0 disables it. the required division ratio of the peripheral clock is selected using the tb22, tb21 and tb20 bits in the tbc2 register. if the peripheral clock source is switched off when the device enters the power down mode, this will disable the peripheral clock output. f sys /4 f p clks1[1:0 ] f sub f sys f h p?es?ale? tb?en tb?[?:0 ] f p /? 0 ~ f p /? 7 pck peripheral clock output
rev. 1.00 180 ?a??? ?0? ?01? rev. 1.00 181 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom peripheral clock registers there are two internal registers which control the overall operation of the peripheral clock output. these are the psc1 and tbc2 registers. name bit 7 6 5 4 3 2 1 0 psc1 clks11 clks10 tbc? tb?en tb?? tb?1 tb?0 pck register list psc1 register bit 7 6 5 4 3 2 1 0 name clks11 clks10 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 clks11, clks10: peripheral clock source selection 00: f 01: f /4 10: f 11: f tbc2 register bit 7 6 5 4 3 2 1 0 name tb?en tb?? tb?1 tb?0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb2en: peripheral clock function enable control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 1~0 tb22, tb21, tb20: peripheral clock output division selection 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: f /128
rev. 1.00 180 ?a??? ?0? ?01? rev. 1.00 181 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom serial interface C spia the device contains an independent spi function. it is important not to confuse this independent spi function with the additional one contained within the combined sim function, which is described in another section of this datasheet. this independent spi function will carry the name spia to distinguish it from the other one in the sim. this spia interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices, etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spia interface specifcation can control multiple slave devices from a single master, this device is provided only one scsa pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pins to select the slave devices. spia interface operation the spia interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdia, sdoa, scka and scsa . pins sdia and sdoa are the serial data input and serial data output lines, scka is the serial clock line and scsa is the slave select line. as the spia interface pins are pin-shared with other functions, the spia interface pins must first be selected by configuring the corresponding selection bits in the pin-shared function selection registers. the spia interface function is disabled or enabled using the spiaen bit in the spiac0 register. communication between devices connected to the spia interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock/signal. as the device only contains a single scsa pin only one slave device can be utilised. the scsa pin is controlled by the application program, set the the sacsen bit to 1 to enable the scsa pin function and clear the sacsen bit to 0 to place the scsa pin into an i/o function. spia master/slave connection
rev. 1.00 18? ?a??? ?0? ?01? rev. 1.00 18? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom

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? ? ? ? - ? ? ? ? ? ??? ? ? ? spia block diagram the spia serial interface function includes the following features: ? full-duplex synchronous data transfer ? both master and slave mode ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spia interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as sacsen and spiaen. spia registers there are three registers which control the overall operation of the spia interface. these are the spiad data registers and two control registers spiac0 and spiac1. register name bit 7 6 5 4 3 2 1 0 spiac0 saspi? saspi1 saspi0 spiaen spiac1 sackpol sackeg sa?ls sacsen sawcol satrf spiad d7 d6 d5 d4 d? d? d1 d0 spia registers list the spiad register is used to store the data being transmitted and received. before the device writes data to this spia bus, the actual data to be transmitted must be placed in the spiad register. after the data is received from the spia bus, the device can read it from the spiad register. any transmission or reception of data from the spia bus must be made via the spiad registers.
rev. 1.00 18? ?a??? ?0? ?01? rev. 1.00 18? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom spiad register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por unknown there are also two control registers for the spia interface, spiac0 and spiac1. register spiac0 is used to control the enable/disable function and to set the data transmission clock frequency. register spiac1 is used for other control functions such as lsb/msb selection, write collision fag, etc. spiac0 register bit 7 6 5 4 3 2 1 0 name saspi? saspi1 saspi0 spiaen r/w r/w r/w r/w r/w por 1 1 1 0 bit 7~5 saspi2~saspi0: spia master/slave clock select 000: spia master, f /4 001: spia master, f /16 010: spia master, f /64 011: spia master, f 100: spia master, tp0 ccrp match frequency/2 (pfd) 101: spia slave 110: reserved 111: reserved bit 4~2 unimplemented, read as 0 bit 1 spiaen: spia enable or disable 0: disable 1: enable the bit is the overall on/off control for the spia interface. when the spiaen bit is cleared to zero to disable the spia interface, the sdia, sdoa, scka and scsa lines will lose their spi function and the spia operating current will be reduced to a minimum value. when the bit is high, the spia interface is enabled. bit 0 unimplemented, read as 0
rev. 1.00 184 ?a??? ?0? ?01? rev. 1.00 185 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom spiac1 register bit 7 6 5 4 3 2 1 0 name sackpol sackeg sa?ls sacsen sawcol satrf r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 sackpol: determines the base condition of the clock line 0: scka line will be high when the clock is inactive 1: scka line will be low when the clock is inactive the sackpol bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sackpol bit is low, then the scka line will be high when the clock is inactive. bit 4 sackeg: determines the spia scka active clock edge type sackpol=0: 0: scka has high base level with data capture on scka rising edge 1: scka has high base level with data capture on scka falling edge sackpol=1: 0: scka has low base level with data capture on scka falling edge 1: scka has low base level with data capture on scka rising edge the sackeg and sackpol bits are used to setup the way that the clock signal outputs and inputs data on the spia bus. these two bits must be confgured before a data transfer is executed otherwise an erroneous clock edge may be generated. the sackpol bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sackpol bit is low, then the scka line will be high when the clock is inactive. the sackeg bit determines active clock edge type which depends upon the condition of the sackpol bit. bit 3 samls: data shift order 0: the lsb of data is transmitted frst 1: the msb of data is transmitted frst bit 2 sacsen: spia scsa pin control 0: disable 1: enable the sacsen bit is used as an enable/disable for the scsa pin. if this bit is low, then the scsa pin function will be disabled and used as an i/o function. if the bit is high the scsa pin will be enabled and used as a select pin. bit 1 sawcol: spia write collision fag 0: collision free 1: collision detected the sawcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the spiad register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. bit 0 satrf: spia transmit/receive complete fag 0: data is being transferred 1: spia data transmission is completed the satrf bit is the transmit/receive complete fag and is set to 1 automatically when an spia data transmission is completed, but must cleared to 0 by the application program. it can be used to generate an interrupt.
rev. 1.00 184 ?a??? ?0? ?01? rev. 1.00 185 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom spia communication after the spia interface is enabled by setting the spiaen bit high, then in the master mode, when data is written to the spiad register, transmission/reception will begin simultaneously. when the data transfer is complete, the satrf fag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the spiad register will be transmitted and any data on the sdia pin will be shifted into the spiad registers. the master should output a scsa signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scsa signal depending upon the configurations of the sackpol bit and sackeg bit. the accompanying timing diagram shows the relationship between the slave data and scsa signal for various confgurations of the sackpol and sackeg bits. the spia will continue to function even in the idle mode.

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? ? ? ? - ? ? ? ? ?? ? ? ?? ?? ? ???? ??? ??? ? ?? ?? ?? ? ? spia transfer control flowchart
rev. 1.00 186 ?a??? ?0? ?01? rev. 1.00 187 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom d 7 / d 0 d 6 / d 1 d 5 / d ? d 4 / d ? d ? / d 4 d ? / d 5 d 1 / d 6 d 0 / d 7 d 7 / d 0 d 6 / d 1 d 5 / d ? d 4 / d ? d ? / d 4 d ? / d 5 d 1 / d 6 d 0 / d 7 spia maste? mode sdia data ?aptu?e d 7 / d 0 d 6 / d 1 d 5 / d ? d 4 / d ? d ? / d 4 d ? / d 5 d 1 / d 6 d 0 / d 7 ( sdoa not ??ange until fi?st scka edge ) spia slave mode ( sackeg = 0 ) sdia data ?aptu?e d 7 / d 0 d 6 / d 1 d 5 / d ? d 4 / d ? d ? / d 4 d ? / d 5 d 1 / d 6 d 0 / d 7 ( sdoa ??ange as soon as w?iting o??u? ; sdoa = floating if = 1 ) spiaen = 1 ? sacsen = 0 ( exte?nal pull - ?ig? ) w?ite to spiad note : fo? spia slave mode ? if spiaen = 1 and sacsen = 0 ? spia is always enabled and igno?e t?e scka ( sackpol = 1? sackeg = 0 ) sdoa ( = 0 ) scka ( sackpol = 1 ) scka ( sackpol = 0 ) sdoa scka ( = 0? = 0 ) scka ( = 1? = 1 ) scka ( = 0? = ) 1 sdoa ( = 1 ) w?ite to spiad w?ite to spiad spia slave mode ( sackeg = 1 ) scsa sackpol sackeg sackpol sackeg sackpol sackeg sackeg sackeg spiaen = 1 ? sacsen = 1 scsa scsa sdia data ?aptu?e scka ( sackpol = 1 scka ( sackpol = 0 sdoa scsa ) ) scsa level. spia master/slave modetiming diagram
rev. 1.00 186 ?a??? ?0? ?01? rev. 1.00 187 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom spia bus enable/disable to enable the spia bus, set sacsen=1 and scsa =0, then wait for data to be written into the spiad (txrx buffer) register. for the master mode, after data has been written to the spiad (txrx buffer) register, then transmission or reception will start automatically. when all the data has been transferred the satrf bit should be set. for the slave mode, when clock pulses are received on scka, data in the txrx buffer will be shifted out or data on sdia will be shifted in. to disable the spia bus scka, sdia, sdoa, scsa will become i/o pins or other pin-shared functions. spia operation all communication is carried out using the 4-line interface for either master or slave mode. the sacsen bit in the spiac1 register controls the overall function of the spia interface. setting this bit high will enable the spia interface by allowing the scsa line to be active, which can then be used to control the spia interface. if the sacsen bit is low, the spia interface will be disabled and the scsa line will be an i/o pin or other pin-shared functions and can therefore not be used for control of the spia interface. if the sacsen bit and the spiaen bit in the spiac0 register are set high, this will place the sdia line in a foating condition and the sdoa line high. if in master mode the scka line will be either high or low depending upon the clock polarity selection bit sackpol in the spiac1 register. if in slave mode the scka line will be in a foating condition. if spiaen is low then the bus will be disabled and scsa , sdia, sdoa and scka pins will all become i/o pins or other pin-shared functions. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the spiad register. in the slave mode, the clock signal will be received from an external master device for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode. master mode: ? step 1 select the clock source and master mode using the saspi2~saspi0 bits in the spiac0 control register ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb shifted frst, this must be same as the slave device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register, which will actually place the data into the txrx buffer. then use the scka and scsa lines to output the data. after this go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sawcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt.
rev. 1.00 188 ?a??? ?0? ?01? rev. 1.00 189 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4. slave mode: ? step 1 select the spi slave mode using the saspi2~saspi0 bits in the spiac0 control register ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb shifted frst, this setting must be the same with the master device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register, which will actually place the data into the txrx buffer. then wait for the master clock scka and scsa signal. after this, go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sawcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt. ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4. error detection the sawcol bit in the spiac1 register is provided to indicate errors during data transfer. the bit is set by the spia serial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the spiad register takes place during a data transfer operation and will prevent the write operation from continuing.
rev. 1.00 188 ?a??? ?0? ?01? rev. 1.00 189 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. these devices contain several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int3 and pint pins, while the internal interrupts are generated by various internal functions such as the tms, comparators,time base, lvd, eeprom, sim and the a/d converter. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi4 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global e?i intn pin intne intnf n=0~? compa?ato? cpne cpnf n=0~1 a/d conve?te? ade adf time base tbne tbnf n=0~1 ?ulti-fun?tion ?fne ?fnf n=0~4 si? si?e si?f lvd lve lvf eepro? dee def pint xpe xpf spia spiae spiaf t? tnpe tnpf n=0~5 tnae tnaf n=0~5 tnbe tnbf n=1 interrupt register bit naming conventions
rev. 1.00 190 ?a??? ?0? ?01? rev. 1.00 191 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom interrupt register contents name bit 7 6 5 4 3 2 1 0 integ int?s1 int?s0 int?s1 int?s0 int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e e?i intc1 adf ?f1f ?f0f cp1f ade ?f1e ?f0e cp1e intc? ?f?f tb1f tb0f ?f?f ?f?e tb1e tb0e ?f?e intc? ?f4f int?f int?f ?f4e int?e int?e ?fi0 t?af t?pf tnaf tnpf t?ae t?pe t0ae t0pe ?fi1 t1bf t1af t1pf t1be t1ae t1pe ?fi? si?f t?af t?pf xpf si?e t?ae t?pe xpe ?fi? spiaf def lvf spiae dee lve ?fi4 t5af t5pf t4af t4pf t5ae t5pe t4ae t4pe integ register bit 7 6 5 4 3 2 1 0 name int?s1 int?s0 int?s1 int?s0 int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 int3s1, int3s0: interrupt edge control for int3 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 5~4 int2s1, int2s0: interrupt edge control for int2 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 3~2 int1s1, int1s0: interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0: interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edge
rev. 1.00 190 ?a??? ?0? ?01? rev. 1.00 191 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom intc0 register bit 7 6 5 4 3 2 1 0 name cp0f int1f int0f cp0e int1e int0e e?i r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 cp0f: comparator 0 interrupt request fag 0: no request 1: interrupt request bit 5 int1f: int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f: int0 interrupt request fag 0: no request 1: interrupt request bit 3 cp0e: comparator 0 interrupt control 0: disable 1: enable bit 2 int1e: int1 interrupt control 0: disable 1: enable bit 1 int0e: int0 interrupt control 0: disable 1: enable bit 0 emi: global interrupt control 0: disable 1: enable
rev. 1.00 19? ?a??? ?0? ?01? rev. 1.00 19? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom intc1 register bit 7 6 5 4 3 2 1 0 name adf ?f1f ?f0f cp1f ade ?f1e ?f0e cp1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adf: a/d converter interrupt request fag 0: no request 1: interrupt request bit 6 mf1f: multi-function interrupt 1 request fag 0: no request 1: interrupt request bit 5 mf0f: multi-function interrupt 0 request fag 0: no request 1: interrupt request bit 4 cp1f: comparator 1 interrupt request fag 0: no request 1: interrupt request bit 3 ade: a/d converter interrupt control 0: disable 1: enable bit 2 mf1e: multi-function interrupt 1 control 0: disable 1: enable bit 1 mf0e: multi-function interrupt 0 control 0: disable 1: enable bit 0 cp1e: comparator 1 interrupt control 0: disable 1: enable
rev. 1.00 19? ?a??? ?0? ?01? rev. 1.00 19? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom intc2 register bit 7 6 5 4 3 2 1 0 name ?f?f tb1f tb0f ?f?f ?f?e tb1e tb0e ?f?e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf3f: multi-function interrupt 3 request fag 0: no request 1: interrupt request bit 6 tb1f: time base 1 interrupt request fag 0: no request 1: interrupt request bit 5 tb0f: time base 0 interrupt request fag 0: no request 1: interrupt request bit 4 mf2f: multi-function interrupt 2 request fag 0: no request 1: interrupt request bit 3 mf3e: multi-function interrupt 3 control 0: disable 1: enable bit 2 tb1e: time base 1 interrupt control 0: disable 1: enable bit 1 tb0e: time base 0 interrupt control 0: disable 1: enable bit 0 mf2e: multi-function interrupt 2 control 0: disable 1: enable
rev. 1.00 194 ?a??? ?0? ?01? rev. 1.00 195 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom intc3 register bit 7 6 5 4 3 2 1 0 name ?f4f int?f int?f ?f4e int?e int?e r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 mf4f: multi-function interrupt 4 request fag 0: no request 1: interrupt request bit 5 int3f: int3 interrupt request fag 0: no request 1: interrupt request bit 4 int2f: int2 interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 mf4e: multi-function interrupt 4 control 0: disable 1: enable bit 1 int3e: int3 interrupt control 0: disable 1: enable bit 0 int2e: int2 interrupt control 0: disable 1: enable
rev. 1.00 194 ?a??? ?0? ?01? rev. 1.00 195 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom mfi0 register bit 7 6 5 4 3 2 1 0 name t?af t?pf t0af t0pf t?ae t?pe t0ae t0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t2af: tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t2pf: tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t0af: tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf: tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t2ae: tm2 comparator a match interrupt control 0: disable 1: enable bit 2 t2pe: tm2 comparator p match interrupt control 0: disable 1: enable bit 1 t0ae: tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe: tm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 196 ?a??? ?0? ?01? rev. 1.00 197 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom mfi1 register bit 7 6 5 4 3 2 1 0 name t1bf t1af t1pf t1be t1ae t1pe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 t1bf: tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 5 t1af: tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf: tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 t1be: tm1 comparator b match interrupt control 0: disable 1: enable bit 1 t1ae: tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe: tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 196 ?a??? ?0? ?01? rev. 1.00 197 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom mfi2 register bit 7 6 5 4 3 2 1 0 name si?f t?af t?pf xpf si?e t?ae t?pe xpe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 simf: sim interrupt request fag 0: no request 1: interrupt request bit 6 t3af: tm3 comparator a match interrupt request fag 0: no request 1: interrupt request bit 5 t3pf: tm3 comparator p match interrupt request fag 0: no request 1: interrupt request bit 4 xpf: external peripheral interrupt request fag 0: no request 1: interrupt request bit 3 sime: sim interrupt control 0: disable 1: enable bit 2 t3ae: tm3 comparator a match interrupt control 0: disable 1: enable bit 1 t3pe: tm3 comparator p match interrupt control 0: disable 1: enable bit 0 xpe: external peripheral interrupt control 0: disable 1: enable
rev. 1.00 198 ?a??? ?0? ?01? rev. 1.00 199 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom mfi3 register bit 7 6 5 4 3 2 1 0 name spiaf def lvf spiae dee lve r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 spiaf: spia interrupt request fag 0: no request 1: interrupt request bit 5 def: data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf: lvd interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 spiae: spia interrupt control 0: disable 1: enable bit 1 dee: data eeprom interrupt control 0: disable 1: enable bit 0 lve: lvd interrupt control 0: disable 1: enable
rev. 1.00 198 ?a??? ?0? ?01? rev. 1.00 199 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom mfi4 register bit 7 6 5 4 3 2 1 0 name t5af t5pf t4af t4pf t5ae t5pe t4ae t4pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t5af: tm5 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t5pf: tm5 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t4af: tm4 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t4pf: tm4 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t5ae: tm5 comparator a match interrupt control 0: disable 1: enable bit 2 t5pe: tm5 comparator p match interrupt control 0: disable 1: enable bit 1 t4ae: tm4 comparator a match interrupt control 0: disable 1: enable bit 0 t4pe: tm4 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 ?00 ?a??? ?0? ?01? rev. 1.00 ?01 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom interrupt operation int0 pin int1 pin int0f int1f int0e int1e e?i 04h e?i 08h ?. fun?t. 0 ?f0f ?f0e 0ch 10h 14h time base 0 tb0f tb0e 18h spia spiaf spiae 1ch inte??upt name request flags enable bits ?aste? enable vector e?i auto disabled in isr p?io?ity hig? low t?1 p t1pf t1pe t?1 a t1af t1ae ?. fun?t. 1 ?f1f ?f1e t?0 p t0pf t0pe t?0 a t0af t0ae inte??upts ?ontained wit?in ?ulti-fun?tion inte??upts xxe enable bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr e?i e?i ?. fun?t. ? ?f?f ?f?e eepro? def dee e?i t?? p t?pf t?pe t?? a t?af t?ae t?1 b t1bf t1be time base 1 tb1f tb1e e?i e?i compa?ato? 0 cp0f cp0e compa?ato? 1 cp1f cp1e a/d adf ade ?0h e?i ?4h ?8h ?ch e?i e?i e?i ?0h e?i ?4h ?8h e?i e?i ?. fun?t. ? ?f?f ?f?e ?. fun?t. 4 ?f4f ?f4e int? pin int? pin int?f int?f int?e int?e xpf xpe t?? p t?pf t?pe t?? a t?af t?ae si? si?f si?e lvd lvf lve t?5 p t5pf t5pe t?5 a t5af t5ae t?4 p t4pf t4pe t?4 a t4af t4ae pint pin interrupt structure
rev. 1.00 ?00 ?a??? ?0? ?01? rev. 1.00 ?01 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom external interrupt the external interrupts are controlled by signal transitions on the pins int0~int3. an external interrupt request will take place when the external interrupt request fags, int0f~int3f are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int3e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int3f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. comparator interrupt the comparator interrupts are controlled by the two internal comparators. a comparator interrupt request will take place when the comparator interrupt request flags, cp0f or cp1f, are set, a situation that will occur when the comparator output changes state. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bits, cp0e and cp1e, must frst be set. when the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt within these devices are five multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, sim interrupt, external peripheral interrupt, lvd interrupt and eeprom interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf5f, are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request flag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt fags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi- function interrupts, namely the tm interrupts, eeprom interrupt and lvd interrupt will not be automatically reset and must be manually reset by the application program.
rev. 1.00 ?0? ?a??? ?0? ?01? rev. 1.00 ?0? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupt the function of the time base interrupt is to provide regular time signal in the form of an internal interrupt. it is controlled by the overflow signal from its internal timer. when this happens its interrupt request fag, tbnf, will be set. to allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bit, tbne, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to its respective vector location will take place. when the interrupt is serviced, the interrupt request flag, tbnf, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. its clock source, f tb , originates from the internal clock source f sub , f sys /4, f sys or f h and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc0 and tbc1 registers to obtain longer interrupt periods whose value ranges. the clock source which in turn controls the time base interrupt period is selected using the clks01 and clks00 bits in the psc0 register. f sys /4 f tb clks0[1:0 ] f sub f sys f h p?es?ale? tb0en tb0[?:0 ] f p /? 8 ~ f p /? 15 tb1en time base 0 inte??upt tb1[?:0 ] time base 1 inte??upt time base interrupt
rev. 1.00 ?0? ?a??? ?0? ?01? rev. 1.00 ?0? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom psc0 register bit 7 6 5 4 3 2 1 0 name clks01 clks00 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 clks01~clks00: time base clock source selection 00: f 01: f /4 10: f tb 11: f tbc0 register bit 7 6 5 4 3 2 1 0 name tb0on tb0? tb01 tb00 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb0on: time base 0 enable/disable control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2~0 tb02~tb00: time base 0 time-out period 000: 2 /f tb 001: 2 9 /f tb 010: 2 10 /f tb 011: 2 /f tb 100: 2 12 /f tb 101: 2 13 /f tb 110: 2 /f tb 111: 2 15 /f tb tbc1 register bit 7 6 5 4 3 2 1 0 name tb1on tb1? tb11 tb10 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb1on: time base 1 enable/disable control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2~0 tb12~tb10: time base 1 time-out period 000: 2 /f tb 001: 2 9 /f tb 010: 2 10 /f tb 011: 2 /f tb 100: 2 12 /f tb 101: 2 13 /f tb 110: 2 /f tb 111: 2 15 /f tb
rev. 1.00 ?04 ?a??? ?0? ?01? rev. 1.00 ?05 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom serial interface module interrupts the serial interface module interrupt, also known as the sim interrupt, is contained within the multi-function interrupt. a sim interrupt request will take place when the sim interrupt request fag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, and muti-function interrupt enable bits, must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the sim interface, a subroutine call to the respective multi-function interrupt vector, will take place. when the serial interface interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the simf fag will not be automatically cleared, it has to be cleared by the application program. spia interface interrupt the spia interface interrupt is contained within the multi-function interrupt. a spia interrupt request will take place when the spia interrupt request fag, spiaf, is set, which occurs when a byte of data has been received or transmitted by the spia interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the spia interface interrupt enable bit, spiae, and muti-function interrupt enable bits, must first be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the spia interface, a subroutine call to the respective multi-function interrupt vector, will take place. when the spia interface interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the spiaf fag will not be automatically cleared, it has to be cleared by the application program. external peripheral interrupt the external peripheral interrupt operates in a similar way to the external interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt request fag, xpf, is set, which occurs when a negative edge transition appears on the pint pin. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, external peripheral interrupt enable bit, xpe, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a negative transition appears on the external peripheral interrupt pin, a subroutine call to the respective multi-function interrupt, will take place. when the external peripheral interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the xpf fag will not be automatically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with different functions. it must therefore be properly confgured to enable it to operate as an external peripheral interrupt pin.
rev. 1.00 ?04 ?a??? ?0? ?01? rev. 1.00 ?05 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom eeprom interrupt the eeprom interrupt, is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom write cycle ends. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom write cycle ends, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. an lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the lvf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact tm has two interrupts, while the enhanced type tm has three interrupts. all of the tm interrupts are contained within the multi-function interrupts. for the compact type tm there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. for the enhanced type tm there are three interrupt request fags tnpf, tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program.
rev. 1.00 ?06 ?a??? ?0? ?01? rev. 1.00 ?07 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though these devices are in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in the sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 ?06 ?a??? ?0? ?01? rev. 1.00 ?07 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom low voltage detector C lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be determined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 lvd output flag 0: no low voltage detected 1: low voltage detected bit 4 low voltage detector enable/disable 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.00 ?08 ?a??? ?0? ?01? rev. 1.00 ?09 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.0v and 4.0v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low voltage detector also has its own interrupt which is contained within one of the multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.00 ?08 ?a??? ?0? ?01? rev. 1.00 ?09 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom scom function for lcd the devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with the pc0~pc1, pc6~pc7 pins. the lcd signals (com and seg) are generated using the application program. lcd operation an external lcd panel can be driven using this device by configuring the pc0~pc1, pc6~pc7 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1/2 bias operation. the scomen bit in the scomc register is the overall master control for the lcd driver. the lcd scomn pin is selected to be used for lcd driving by the corresponding pin-shared function selection bits. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation.

lcd com bias lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the scomc register. scomc register bit 7 6 5 4 3 2 1 0 name d7 isel1 isel0 sco?en r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 reserved bit 0: correct level - bit must be reset to zero for correct operation 1: unpredictable operation - bit must not be set high bit 6~5 select scom typical bias current (v dd =5v) 00: 25a 01: 50a 10: 100a 11: 200a bit 4 scom module control 0: disable 1: enable bit 3~0 unimplemented, read as 0
rev. 1.00 ?10 ?a??? ?0? ?01? rev. 1.00 ? 11 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom confguration options confguration options refer to certain options within the mcu that are programmed into the devices during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the devices using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options 1 hig? speed system os?illato? sele?tion C f h hxt ? erc o? hirc ? low speed system os?illato? sele?tion C f sub lxt o ? lirc ? i/o o? reset pin sele?tion reset pin o? i/o pin application circuits vdd pb0/res vss pb1/osc1 pb?/osc? pb?/xt1 pb4/xt? osc ci??uit osc ci??uit 100k 0.1uf 0.1uf pc0~pc7 pd0~pd7 pe0~pe7 pf0~pf7 pg0~pg7 ph0~ph5 v dd pb0~pb7 pa0~pa7
rev. 1.00 ?10 ?a??? ?0? ?01? rev. 1.00 ? 11 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of several kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions such as inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 ?1? ?a??? ?0? ?01? rev. 1.00 ?1? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 ?1? ?a??? ?0? ?01? rev. 1.00 ?1? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom instruction set summary the instructions related to the data memory access in the following table can be used when the desired data memory is located in data memory section 0. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a?[m] add data ?emo? y to acc 1 z? c? ac? ov ? sc add? a?[m] add acc to data ?emo?y 1 note z? c? ac? ov ? sc add a?x add immediate data to acc 1 z? c? ac? ov ? sc adc a?[m] add data ?emo? y to acc wit? ca??y 1 z? c? ac? ov ? sc adc? a?[m] add acc to data memo ?y wit? ca??y 1 note z? c? ac? ov ? sc sub a?x subt?a?t immediate data f?om t? e acc 1 z? c? ac? ov ? sc? cz sub a?[m] subt?a?t data ?emo?y f? om acc 1 z? c? ac? ov ? sc? cz sub? a?[m] subt?a?t data ?emo?y f? om acc wit? ?esult in data ?emo?y 1 note z? c? ac? ov ? sc? cz sbc a?x subt?a?t immediate data f? om acc wit? ca??y 1 z? c? ac? ov ? sc? cz sbc? a?[m] subt?a?t data ?emo?y f? om acc wit? ca??y ? ?esult in data ?emo?y 1 note z? c? ac? ov ? sc? cz daa [m] de? imal adjust acc fo? addition wit? ?esult in data ?emo?y 1 note c logic operation and a?[m] logi? al and data ?emo? y to acc 1 z or a?[m] logi?al or data ?emo? y to acc 1 z xor a?[m] logi?al xor data ?emo? y to acc 1 z and? a?[m] logi? al and acc to data ?emo?y 1 note z or? a?[m] logi? al or acc to data ?emo?y 1 note z xor? a?[m] logi? al xor acc to data ?emo?y 1 note z and a?x logi? al and immediate data to acc 1 z or a?x logi? al or immediate data to acc 1 z xor a?x logi? al xor immediate data to acc 1 z cpl [m] complement data ?emo?y 1 note z cpla [m] complement data ?emo?y wit? ? esult in acc 1 z increment & decrement inca [m] in??ement data ?emo?y wit? ? esult in acc 1 z inc [m] in??ement data ?emo?y 1 note z deca [m] de??ement data ?emo?y wit? ? esult in acc 1 z dec [m] de??ement data ?emo?y 1 note z rotate rra [m] rotate data ?emo?y ?ig?t wit? ? esult in acc 1 none rr [m] rotate data ?emo?y ?ig?t 1 note none rrca [m] rotate data ?emo?y ?ig?t t??oug? ca??y wit? ? esult in acc 1 c rrc [m] rotate data ?emo?y ?ig?t t??oug? ca??y 1 note c rla [m] rotate data ?emo?y left wit? ? esult in acc 1 none rl [m] rotate data ?emo?y left 1 note none rlca [m] rotate data ?emo?y left t??oug? ca??y wit? ? esult in acc 1 c rlc [m] rotate data ?emo?y left t??oug? ca??y 1 note c
rev. 1.00 ?14 ?a??? ?0? ?01? rev. 1.00 ?15 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom mnemonic description cycles flag affected data move ? ov a?[m] ?ove data ?emo? y to acc 1 none ?ov [m]?a ? ove acc to data ?emo?y 1 note none ? ov a?x ? ove immediate data to acc 1 none bit operation clr [m].i clea? bit of data ?emo?y 1 note none set [m].i set bit of data ?emo?y 1 note none branch j? p add? jump un?onditionally ? none sz [m] skip if data ?emo?y is ze?o 1 note none sza [m] skip if data ?emo?y is ze?o wit? data movement to acc 1 note none sz [m].i skip if bit i of data ?emo?y is ze?o 1 note none snz [m] skip if data ?emo?y is not ze?o 1 note none siz [m] skip if in??ement data ?emo?y is ze?o 1 note none sdz [m] skip if de??ement data ?emo?y is ze?o 1 note none siza [m] skip if in??ement data ?emo?y is ze?o wit? ? esult in acc 1 note none sdza [m] skip if de??ement data ?emo?y is ze?o wit? ? esult in acc 1 note none call add ? sub?outine ?all ? none ret retu?n f?om sub?outine ? none ret a ?x retu?n f?om sub? outine and load immediate data to acc ? none reti retu?n f?om inte??upt ? none table read tabrd [m] read table to tblh and data ?emo?y ? note none tabrdl [m] read table (last page) to tblh and data ?emo?y ? note none itabrd [m] increment table pointer tblp frst and read table to tblh and data memory ? note none itabrdl [m] increment table pointer tblp frst and read table (last page) to tblh and data ?emo?y ? note none miscellaneous nop no ope?ation 1 none clr [m] clea? data ?emo?y 1 note none set [m] set data ?emo?y 1 note none clr wdt clea? wat?? dog time? 1 to ? pdf swap [m] swap nibbles of data ?emo?y 1 note none swapa [m] swap nibbles of data ?emo?y wit? ? esult in acc 1 none halt ente? powe? down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt instruction the to and pdf fags may be affected by the execution status. the to and pdf fags are cleared after the clr wdt instructions is executed. otherwise the to and pdf fags remain unchanged.
rev. 1.00 ?14 ?a??? ?0? ?01? rev. 1.00 ?15 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom extended instruction set the extended instructions are used to support the full range address access for the data memory. when the accessed data memory is located in any data memory sections except section 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the cpu frmware performance. mnemonic description cycles flag affected arithmetic ladd a?[m] add data ?emo? y to acc ? z? c? ac? ov ? sc ladd? a?[m] add acc to data ?emo?y ? note z? c? ac? ov ? sc ladc a?[m] add data ?emo? y to acc wit? ca??y ? z? c? ac? ov ? sc ladc? a?[m] add acc to data memo ?y wit? ca??y ? note z? c? ac? ov ? sc lsub a?[m] subt?a?t data ?emo?y f? om acc ? z? c? ac? ov ? sc? cz lsub? a?[m] subt?a?t data ?emo?y f? om acc wit? ?esult in data ?emo?y ? note z? c? ac? ov ? sc? cz lsbc a?[m] subt?a?t data ?emo?y f? om acc wit? ca??y ? z? c? ac? ov ? sc? cz lsbc? a?[m] subt?a?t data ?emo?y f? om acc wit? ca??y ? ?esult in data ?emo?y ? note z? c? ac? ov ? sc? cz ldaa [m] de? imal adjust acc fo? addition wit? ?esult in data ?emo?y ? note c logic operation land a?[m] logi? al and data ?emo? y to acc ? z lor a?[m] logi?al or data ?emo? y to acc ? z lxor a?[m] logi?al xor data ?emo? y to acc ? z land? a?[m] logi? al and acc to data ?emo?y ? note z lor? a?[m] logi? al or acc to data ?emo?y ? note z lxor? a?[m] logi? al xor acc to data ?emo?y ? note z lcpl [m] complement data ?emo?y ? note z lcpla [m] complement data ?emo?y wit? ? esult in acc ? z increment & decrement linca [m] in??ement data ?emo?y wit? ? esult in acc ? z linc [m] in??ement data ?emo?y ? note z ldeca [m] de??ement data ?emo?y wit? ? esult in acc ? z ldec [m] de??ement data ?emo?y ? note z rotate lrra [m] rotate data ?emo?y ?ig?t wit? ? esult in acc ? none lrr [m] rotate data ?emo?y ?ig?t ? note none lrrca [m] rotate data ?emo?y ?ig?t t??oug? ca??y wit? ? esult in acc ? c lrrc [m] rotate data ?emo?y ?ig?t t??oug? ca??y ? note c lrla [m] rotate data ?emo?y left wit? ? esult in acc ? none lrl [m] rotate data ?emo?y left ? note none lrlca [m] rotate data ?emo?y left t??oug? ca??y wit? ? esult in acc ? c lrlc [m] rotate data ?emo?y left t??oug? ca??y ? note c data move l?ov a?[m] ?ove data ?emo? y to acc ? none l?ov [m]?a ? ove acc to data ?emo?y ? note none bit operation lclr [m].i clea? bit of data ?emo?y ? note none lset [m].i set bit of data ?emo?y ? note none
rev. 1.00 ?16 ?a??? ?0? ?01? rev. 1.00 ?17 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom mnemonic description cycles flag affected branch lsz [m] skip if data ?emo?y is ze?o ? note none lsza [m] skip if data ?emo?y is ze?o wit? data movement to acc ? note none lsnz [m] skip if data ?emo?y is not ze?o ? note none lsz [m].i skip if bit i of data ?emo?y is ze?o ? note none lsnz [m].i skip if bit i of data ?emo?y is not ze?o ? note none lsiz [m] skip if in??ement data ?emo?y is ze?o ? note none lsdz [m] skip if de??ement data ?emo?y is ze?o ? note none lsiza [m] skip if in??ement data ?emo?y is ze?o wit? ? esult in acc ? note none lsdza [m] skip if de??ement data ?emo?y is ze?o wit? ? esult in acc ? note none table read ltabrd [m] read table to tblh and data ?emo?y ? note none ltabrdl [m] read table (last page) to tblh and data ?emo?y ? note none litabrd [m] increment table pointer tblp frst and read table to tblh and data memory ? note none litabrdl [m] increment table pointer tblp frst and read table (last page) to tblh and data ?emo?y ? note none miscellaneous lclr [m] clea? data ?emo?y ? note none lset [m] set data ?emo?y ? note none lswap [m] swap nibbles of data ?emo?y ? note none lswapa [m] swap nibbles of data ?emo?y wit? ? esult in acc ? none note: 1. for these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. any extended instruction which changes the contents of the pcl register will also require three cycles for execution.
rev. 1.00 ?16 ?a??? ?0? ?01? rev. 1.00 ?17 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom instruction defnition adc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c, sc adcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c, sc add a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c, sc add a,x add immediate data to acc description the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. operation acc acc + x affected fag(s) ov, z, ac, c, sc addm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c, sc and a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specifed immediate data perform a bit wise logical and operation. the result is stored in the accumulator. operation acc acc and x affected fag(s) z andm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z
rev. 1.00 ?18 ?a??? ?0? ?01? rev. 1.00 ?19 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom call addr subroutine call description unconditionally calls a subroutine at the specifed address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specifed address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruction. operation stack program counter + 1 program counter addr affected fag(s) none clr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none clr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none clr wdt clear watchdog timer description the to, pdf fags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt2 and must be executed alternately with clr wdt2 to have effect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed alternately with clr wdt1 to have effect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf cpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z
rev. 1.00 ?18 ?a??? ?0? ?01? rev. 1.00 ?19 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom cpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c dec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down fag pdf is set and the wdt time-out fag to is cleared. operation to 0 pdf 1 affected fag(s) to, pdf inc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z
rev. 1.00 ??0 ?a??? ?0? ?01? rev. 1.00 ??1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom jmp addr jump unconditionally description the contents of the program counter are replaced with the specifed address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected fag(s) none mov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none mov a,x move immediate data to acc description the immediate data specifed is loaded into the accumulator. operation acc x affected fag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected fag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z or a,x logical or immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected fag(s) z orm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the restored address. operation program counter stack affected fag(s) none
rev. 1.00 ??0 ?a??? ?0? ?01? rev. 1.00 ??1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specifed immediate data. program execution continues at the restored address. operation program counter stack acc x affected fag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by setting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected fag(s) none rl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none rla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none rlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c rr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none
rev. 1.00 ??? ?a??? ?0? ?01? rev. 1.00 ??? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom rra [m] rotate data memory right with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none rrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c sbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz sbc a, x subtract immediate data from acc with carry description the immediate data and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc - [m] - c affected fag(s) ov, z, ac, c, sc, cz sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz
rev. 1.00 ??? ?a??? ?0? ?01? rev. 1.00 ??? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom sdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none set [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none snz [m].i skip if data memory is not 0 description if the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none
rev. 1.00 ??4 ?a??? ?0? ?01? rev. 1.00 ??5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom snz [m] skip if data memory is not 0 description if the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m] 0 affected fag(s) none sub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c, sc, cz subm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c, sc, cz sub a,x subtract immediate data from acc description the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? x affected fag(s) ov, z, ac, c, sc, cz swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none sz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none
rev. 1.00 ??4 ?a??? ?0? ?01? rev. 1.00 ??5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom sza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none tabrd [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none itabrd [m] increment table pointer low byte frst and read table to tblh and data memory description increment table pointer low byte, tblp, frst and then the program code addressed by the table pointer (tbhp and tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none itabrdl [m] increment table pointer low byte frst and read table (last page) to tblh and data memory description increment table pointer low byte, tblp, frst and then the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z
rev. 1.00 ??6 ?a??? ?0? ?01? rev. 1.00 ??7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom xorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected fag(s) z
rev. 1.00 ??6 ?a??? ?0? ?01? rev. 1.00 ??7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom extended instruction defnition the extended instructions are used to directly access the data stored in any data memory sections. ladc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c, sc ladcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c, sc ladd a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c, sc laddm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c, sc land a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z landm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z lclr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none lclr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none
rev. 1.00 ??8 ?a??? ?0? ?01? rev. 1.00 ??9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom lcpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z lcpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z ldaa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c ldec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z ldeca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z linc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z linca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z
rev. 1.00 ??8 ?a??? ?0? ?01? rev. 1.00 ??9 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom lmov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none lmov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none lor a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z lorm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z lrl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none lrla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none lrlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c lrlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c
rev. 1.00 ??0 ?a??? ?0? ?01? rev. 1.00 ??1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom lrr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none lrra [m] rotate data memory right with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none lrrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c lrrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c lsbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz lsbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz
rev. 1.00 ??0 ?a??? ?0? ?01? rev. 1.00 ??1 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom lsdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none lsdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none lset [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none lsiz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none lsiza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none lsnz [m].i skip if data memory is not 0 description if the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none
rev. 1.00 ??? ?a??? ?0? ?01? rev. 1.00 ??? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom lsnz [m] skip if data memory is not 0 description if the content of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m] 0 affected fag(s) none lsub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c, sc, cz lsubm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c, sc, cz lswap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none lswapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none lsz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none lsza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none
rev. 1.00 ??? ?a??? ?0? ?01? rev. 1.00 ??? ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom lsz [m].i skip i f bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none ltabrd [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none ltabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none litabrd [m] increment table pointer low byte frst and read table to tblh and data memory description increment table pointer low byte, tblp, frst and then the program code addressed by the table pointer (tbhp and tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none litabrdl [m] increment table pointer low byte frst and read table (last page) to tblh and data memory description increment table pointer low byte, tblp, frst and then the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none lxor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z lxorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z
rev. 1.00 234 march 20, 2013 rev. 1.00 235 march 20, 2013 HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information ? pb free products ? green packages products
rev. 1.00 ??4 ?a??? ?0? ?01? rev. 1.00 ??5 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.?50 D 0.?58 b 0.?7? D 0.?80 c 0.?50 D 0.?58 d 0.?7? D 0.?80 e D 0.0?0 D f D 0.008 D g 0.05? D 0.057 h D D 0.06? i D 0.004 D j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.50 D f D 0.?0 D g 1.?5 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.?0 0 D 7
rev. 1.00 ??6 ?a??? ?0? ?01? rev. 1.00 ??7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom 64-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.?50 D 0.?58 b 0.?7? D 0.?80 c 0.?50 D 0.?58 d 0.?7? D 0.?80 e D 0.016 D f 0.005 D 0.009 g 0.05? D 0.057 h D D 0.06? i 0.00? D 0.006 j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.40 D f 0.1? D 0.?? g 1.?5 D 1.45 h D D 1.60 i 0.05 D 0.15 j 0.45 D 0.75 k 0.09 D 0.?0 0 D 7
rev. 1.00 ??6 ?a??? ?0? ?01? rev. 1.00 ??7 ?a??? ?0? ?01? HT66F60A/ht66f70a enhanced a/d flash type 8-bit mcu with eeprom holtek semiconductor inc. (headquarters) no.?? c?eation rd. ii? s?ien?e pa?k? hsin??u? taiwan tel: 886- ?-56?-1999 fax: 886-?-56? -1189 ? ttp://www.?oltek.?om.tw holtek semiconductor inc. (taipei sales offce) 4f-?? no. ?-?? yuanqu st.? nankang softwa?e pa?k? taipei 115? taiwan tel: 886- ?-?655-7070 fax: 886-?-?655-7?7? fax: 886-?-?655-7?8? (inte?national sales ?otline) holtek semiconductor (china) inc. (dongguan sales offce) building no.10? xinz?u cou?t? (no.1 headqua?te?s)? 4 cuiz?u road? songs?an lake? dongguan? c?ina 5??808 tel: 86-769- ?6?6-1?00 fax: 86-769-?6?6-1? 11? 86-769-?6?6-1??? holtek semiconductor (usa), inc. (north america sales offce) 467?9 f?emont blvd.? f?emont? ca 945?8? usa tel: 1-510- ?5?-9880 fax: 1-510-?5?-9885 ? ttp://www.?oltek.?om copy?ig?t ? ?01? by holtek se? iconductor inc. t ? e info? mation appea?ing in t ? is data s? eet is believed to be a??u? ate at t ? e time of publi? ation. howeve ?? holtek assumes no ? esponsibility a ? ising f ? om t ? e use of t ? e spe? ifi ? ations des ?? ibed. t?e appli?ations mentioned ?e?ein a?e used solely fo? t?e pu?pose of illust? ation and holtek makes no wa?? anty o? ?ep? esentation t ? at su?? appli? ations will be suitable wit ? out fu?t ?e? modifi? ation? no? ?e? ommends t? e use of its p?odu? ts fo? appli? ation t? at may p? esent a ? isk to ? uman life due to malfun?tion o? ot?e?wise. holtek's p?odu?ts a?e not aut?o?ized fo? use as ??iti?al ? omponents in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for t?e most up-to-date info?mation? please visit ou? web site at ? ttp://www.?oltek.?om.tw .

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